莱迪思解决方案

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  • Image Signal Processing IP Cores Suite

    IP Core

    Image Signal Processing IP Cores Suite

    The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
    Image Signal Processing IP Cores Suite
  • GHRD/GSRD参考设计

    Reference Design

    GHRD/GSRD参考设计

    黄金硬件和软件参考设计(GSRD)包括了使用基于CertusPro-NX Versa开发板开发各种应用所需的组件。
  • GHRD/GSRD Demonstration

    演示

    GHRD/GSRD Demonstration

    The Golden Hardware and Software Reference Design comprises of components for developing various kind of applications using CertusPro-NX Versa Board.
    GHRD/GSRD Demonstration
  • MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

    演示

    MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

    This demo illustrates L-ASC10 integration in a MachXO5-NX design and demonstrates RISC-V SOC interfacing with power sequencing and fault response.
    MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration
  • 莱迪思图像信号处理演示

    演示

    莱迪思图像信号处理演示

    为嵌入式视觉开发套件提供基于ECP5 FPGA的完整ISP示例设计,非常适合工业、医疗和汽车应用。
    莱迪思图像信号处理演示
  • 拥有故障记录功能的电源时序演示

    演示

    拥有故障记录功能的电源时序演示

    使用L-ASC10监视和控制来自中心控制点的四个独立电源平面。带时间戳的故障记录。可扩展。
    拥有故障记录功能的电源时序演示
  • Crosslink-NX PCIe桥接板上的PCIe基础演示

    演示

    Crosslink-NX PCIe桥接板上的PCIe基础演示

    该PCIe基础演示可以控制三个7段LED,并通过PCIe插槽操作FPGA的片上存储器。
    Crosslink-NX PCIe桥接板上的PCIe基础演示
  • PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    演示

    PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    PCIe Colorbar Demo displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.
    PCIe Colorbar Demo for Lattice Nexus-based FPGAs
  • PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    演示

    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.
    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs
  • 基于莱迪思Nexus FPGA的PCIe多功能演示

    演示

  • 莱迪思Sentry MachXO3D可信根演示

    演示

    莱迪思Sentry MachXO3D可信根演示

    完整的位流/固件包可帮助您在采用MachXO3D的莱迪思Sentry演示板上演示和测试符合NIST 800-193规范的PFR解决方案
    莱迪思Sentry MachXO3D可信根演示
  • PCI Express for Nexus FPGAs

    IP Core

    PCI Express for Nexus FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express for Nexus FPGAs
  • RISC-V MC CPU IP核

    IP Core

    RISC-V MC CPU IP核

    Propel IP模块:具有可选的定时器和PIC子模块的32位RISC-V处理器核,通过AHB-Lite总线连接到其他Propel各类IP模块。
    RISC-V MC CPU IP核
  • RISC-V SM CPU IP核

    IP Core

    RISC-V SM CPU IP核

    RISC-V SM CPU IP可以在处理数据和指令时处理外部中断。该IP支持RV32I指令集、外部中断和调试,遵循JTAG – IEEE 1149.1标准。
    RISC-V SM CPU IP核
  • RISC-V RX CPU IP核

    IP Core

    RISC-V RX CPU IP核

    莱迪思RISC-V RX IP使用32位RISC-V处理器核和多个子模块,在监控外部中断的同时处理数据和指令。
    RISC-V RX CPU IP核
  • PCI Express for Avant and Nexus 2 FPGAs

    IP Core

    PCI Express for Avant and Nexus 2 FPGAs

    The Lattice PCIe X8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express for Avant and Nexus 2 FPGAs
  • RISC-V Nano CPU IP Core

    IP Core

    RISC-V Nano CPU IP Core

    The RISC-V Nano CPU IP contains a 32-bit RISC-V processor core that supports the RV32I instruction set and a lightweight interrupt merge controller.
    RISC-V Nano CPU IP Core
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory (TCM) IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Tightly-Coupled Memory (TCM) IP Core
  • RISC-V AXI4 I/O Physical Memory Protection (IOPMP) IP Core

    IP Core

    RISC-V AXI4 I/O Physical Memory Protection (IOPMP) IP Core

    RISC-V I/O Memory Protection IP protects the data in specific memory regions and allows the CPU to control external AXI manager access to AXI subordinates at run-time.
    RISC-V AXI4 I/O Physical Memory Protection (IOPMP) IP Core
  • Lattice Sentry I2C Filter IP Core

    IP Core

    Lattice Sentry I2C Filter IP Core

    Sentry I2C Filter IP Core provides an interface between I2C bus devices and a host processor while protecting against common I2C bus vulnerabilities.
    Lattice Sentry I2C Filter IP Core
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