Software Defined Radio

Low Power Solutions for Next Generation Communications Systems

Software Defined Radios (SDR) provide a flexible and programmable communication platform by combining the RF front-end to a digital signal processor. Lattice FPGAs provide a high level of programmability, reconfigurability and control that results in optimized system performance with break-through reduction in system power and size. Lattice FPGAs provide a seamless interface to industry leading RF components to lower development risk and time-to-market. Lattice FPGA resources are optimized with signal processing and memory blocks that are required to implement many waveform types, wide operating frequency bands and wide operating temperature range without the need for cooling.

Lattice’s offers DSP and interface IP, tools and reference designs to enable a plethora of possible solutions and architectures. To accelerate time to market, developers can start with PC based plug-in cards equipped with Lattice FPGAs to capture and manipulate waveforms or to optimize the employed algorithms. Within the FPGA, high bandwidth interfaces offer the ability to transfer blocks of data with low latency using direct memory access from RF sub-system to memory, processing and higher layer system CPU.

Features

  • Up to 1800 DSP blocks and 1000 memory blocks for high performance signal processing
  • Support for high speed Interfaces such as JESD204BC
  • Low Power architectures eliminates thermal challenges
  • Small Form factor packages simplify integration of advanced radio functions

Software Defined Radio

Jump to

Block Diagram

Low Power Programmable Radio Solution

  • Hardware and software platform to implement key signal processing features
  • Complete and robust radio solution in a small form factor
  • Open source stack with support for GNU radio

Example Applications

RF Sensing and Processing Solution

  • Support for JESD204B/C and high speed LVDS connectivity to RF
  • Interoperable with wide variety of common RF front-ends
  • Up to 25Gbps per lane of robust data transfer over backplane and connectors
  • Support for direct Streaming interface from memory over Ethernet

控制平面安全和硬件管理

  • 通过PCIe将CPU桥接到多个控制平面外设(I2C、UART、GPIO)、电路板管理功能和10GE控制平面通信
  • 在FPGA上实现安全功能(例如加密、身份验证)有助于保护控制平面通信
  • 10G SERDES支持 PCIe Gen 3 x 4(硬核 IP)和10 Gb以太网(硬核IP实现10GBASE-R PCS)
  • 由于采用FD-SOI技术,软错误率(SER)降低100倍,可实现极高的系统稳定性和长时间正常运行
  • FPGA快速配置支持电路板管理需求和PCIe启动时间要求

Reference Design

5G Small Cell PCIe to JESD204B Bridge Reference Design

Reference Design

5G Small Cell PCIe to JESD204B Bridge Reference Design

5G Mid-Power Integrated Small Cell, reference platform is a comprehensive development board tailored for 5G baseband processors and transceiver frontends.
5G Small Cell PCIe to JESD204B Bridge Reference Design
莱迪思ORAN IEEE 1588 PTP安全同步参考设计

Reference Design

莱迪思ORAN IEEE 1588 PTP安全同步参考设计

莱迪思ORAN 1.1参考设计展示了如何提供高度可靠的时间同步和相位对齐,从而在5G ORAN网络中实现精确的定时。
莱迪思ORAN IEEE 1588 PTP安全同步参考设计
冗余电源管理

Reference Design

冗余电源管理

Uses a Lattice Power Manager II device to achieve Redundant Power Supply Management using the power supply OR’ing technique
冗余电源管理
JESD204 ADC参考设计

Reference Design

JESD204 ADC参考设计

Provides designers an ideal platform for a low cost, low power and small footprint solution for FPGA based serial data acquisition and processing
JESD204 ADC参考设计

Demo

MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

演示

MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

This demo illustrates L-ASC10 integration in a MachXO5-NX design and demonstrates RISC-V SOC interfacing with power sequencing and fault response.
MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration
拥有故障记录功能的电源时序演示

演示

拥有故障记录功能的电源时序演示

使用L-ASC10监视和控制来自中心控制点的四个独立电源平面。带时间戳的故障记录。可扩展。
拥有故障记录功能的电源时序演示
数字前端(DFE)演示示例

演示

数字前端(DFE)演示示例

Lattice DFE (Digital Front End) demonstration utilizing of CPRI (Common Public Radio Interface), DUC (Digital Up Converter) and CFR (Crest Factor Reduction).
数字前端(DFE)演示示例

IP Cores

FFT 编译器

IP Core

FFT 编译器

The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
FFT 编译器
FIR 滤波器生成器

IP Core

FIR 滤波器生成器

可灵活配置的多通道FIR滤波器。最多支持256个通道,每个拥有2048个抽头。输入和系数宽度为4至32位。
FIR 滤波器生成器
JESD204B IP核

IP Core

JESD204B IP核

莱迪思JESD204B IP核是用于数据转换器和FPGA器件之间的高速串行接口,用于取代传统接口。
JESD204B IP核
10Gb Ethernet MAC+PHY IP Core

IP Core

10Gb Ethernet MAC+PHY IP Core

The Lattice 10G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.
10Gb Ethernet MAC+PHY IP Core
25Gb以太网MAC+PHY IP核

IP Core

25Gb以太网MAC+PHY IP核

莱迪思半导体的25G以太网(GbE)IP核支持在主机处理器和以太网网络之间发送和接收数据。
25Gb以太网MAC+PHY IP核

Development Kits & Boards

LimeSDR Mini Development Board by Lime Microsystems

Board

LimeSDR Mini Development Board by Lime Microsystems

LimeSDR Mini Dev Board is a low cost, open source and apps-enabled SDR platform that can be used to support any type of wireless communication standard.
LimeSDR Mini Development Board by Lime Microsystems

Documentation

资讯资源
标题 编号 版本 日期 格式 文件大小
选择全部
Rapid Prototype Work Flow with HDL Coder - 5G OFDM and Single Tone Modulation Use Case
WP0039 1.0 8/8/2024 PDF 1.8 MB
Comparative Study on Low Power FPGA Solutions
WP0037 1.0 4/23/2024 PDF 2 MB