Software Defined Radio

Low Power Solutions for Next Generation Communications Systems

Our system is going under maintenance starting June 21, 2024 at 8:00 PM Pacific and ending June 23, 2024 at 2:00 PM Pacific. During this window, the website may not be reachable. For immediate assistance, please contact techsupport@latticesemi.com.

相关产品

Software Defined Radios (SDR) provide a flexible and programmable communication platform by combining the RF front-end to a digital signal processor. Lattice FPGAs provide a high level of programmability, reconfigurability and control that results in optimized system performance with break-through reduction in system power and size. Lattice FPGAs provide a seamless interface to industry leading RF components to lower development risk and time-to-market. Lattice FPGA resources are optimized with signal processing and memory blocks that are required to implement many waveform types, wide operating frequency bands and wide operating temperature range without the need for cooling.

Lattice’s offers DSP and interface IP, tools and reference designs to enable a plethora of possible solutions and architectures. To accelerate time to market, developers can start with PC based plug-in cards equipped with Lattice FPGAs to capture and manipulate waveforms or to optimize the employed algorithms. Within the FPGA, high bandwidth interfaces offer the ability to transfer blocks of data with low latency using direct memory access from RF sub-system to memory, processing and higher layer system CPU.

Features

  • Up to 1800 DSP blocks and1000 memory blocks for high performance signal processing
  • Support for high speed Interfaces such as JESD204BC
  • Low Power architectures eliminates thermal challenges
  • Small Form factor packages simplify integration of advanced radio functions

Software Defined Radio Board Photo

Jump to

Block Diagram

Low Power Programmable Radio Solution

  • Hardware and software platform to implement key signal processing features
  • Complete and robust radio solution in a small form factor
  • Open source stack with support for GNU radio

Reference Design

JESD204 ADC参考设计

Reference Design

JESD204 ADC参考设计

Provides designers an ideal platform for a low cost, low power and small footprint solution for FPGA based serial data acquisition and processing
JESD204 ADC参考设计

Demo

数字前端(DFE)演示示例

演示

数字前端(DFE)演示示例

Lattice DFE (Digital Front End) demonstration utilizing of CPRI (Common Public Radio Interface), DUC (Digital Up Converter) and CFR (Crest Factor Reduction).
数字前端(DFE)演示示例

IP Cores

JESD204B IP核

IP Core

JESD204B IP核

Supports ADC/DAC to FPGA in both an Rx and/or a Tx core. The Rx and Tx cores can each be generated separately and with different parameters.
JESD204B IP核
波峰因数减少(Crest Factor Reduction)IP

IP Core

波峰因数减少(Crest Factor Reduction)IP

Reduces the peak-to-average ratio (PAR) of wideband digital signals. Highly configurable - up to 4 antennas with a wide variety of singal processing options.
波峰因数减少(Crest Factor Reduction)IP
JESD204A IP核

IP Core

JESD204A IP核

Supports ADC/DAC to FPGA in both an Rx and/or a Tx core. The Rx and Tx cores can each be generated separately and with different parameters.
JESD204A IP核

Development Kits & Boards