MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

Implement Centralized Platform Management System using Three L-ASC10 Devices

This demo shows how to combine Lattice’s Analog Sense and Control (L-ASC10) devices with Lattice’s MachXO5-NX FPGA. The Demo Design is a centralized Platform Management system using three L-ASC10 devices and has three separate power sequencers (one for each L-ASC10) that are cascaded in both powering-up and powering-down.

The RISC-V in this Demo Design configures the L-ASC10 devices over an I2C bus at initial power up; this illustrates how multiple boot and remote updates can be supported. The firmware APIs interface with the centralized Platform Manager to enable both powering-up and powering-down along with fault monitoring.

Required Tools – Propel Builder, Propel SDK, Diamond's Platform Designer, Radiant, and ASC_HEX_Reader.exe. Propel Builder creates the RISC-V SOC for the MachXO5-NX device.

Features

  • Individual power planes can be sequenced up and down
  • Three power planes are monitored and sequenced from a central control point
  • Build power management design using Lattice’s RISC-V architecture and MachXO5-NX FPGA

Block-Diagram

Documentation

Quick Reference
Downloads
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MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration – User Guide
FPGA-UG-02194 1.0 11/28/2023 PDF 3.8 MB
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MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration – Source Code
11/28/2023 ZIP 42.6 MB

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