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Lattice OCP Ready Solutions for DC-SCM and HPM CPLD Connectivity

Empowering Interoperable, Scalable, and Low-Power Server Management

Lattice Semiconductor offers cutting-edge IP cores and reference designs—LTPI (LVDS Tunneling Protocol & Interface) and MPESTI (Modular Peripheral Sideband Tunneling Interface)—that are fully compliant with OCP DC-SCM 2.0/2.1 specifications, enabling seamless connectivity between Secure Control Modules (SCM) and Host Processor Modules (HPM).

OCP-solution-provider-logo-color-vert-3x-v2-5 

Key Features

OCP Compliant - Graphics
OCP Compliant
Aligns with DC-SCM 2.0/2.1 standards

Modular Scalable - Graphics
Modular & Scalable
Enables flexible, optimized resource; server design and upgrades

Secure & Resilient - Graphics
Secure & Resilient
Root of Trust (RoT) implementations

Validated Ecosystem - Graphics
Validated Ecosystem
Proven interoperability with major server vendors

Jump to

Block Diagram

LPTI BDExpand Image

DC-SCM 2.0 LVDS Tunneling Protocol & Interface (LTPI) Block Diagram

Videos

OCP Overview - Video Thumbnail
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OCP Overview

LVDS Tunneling Protocol & Interface (LTPI) Reference Design Walkthrough-Thumbnail
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LVDS Tunneling Protocol & Interface (LTPI) Reference Design Walkthrough Guide

LVDS Tunneling Protocol & Interface (LTPI) IP Walkthrough-Thumbnail
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LVDS Tunneling Protocol & Interface (LTPI) IP Walkthrough

Virtual Laboratory for Remote Demonstration-Thumbnail
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Virtual Laboratory for Remote Demonstration

Dual Host Processor Module HPM and Single Secure Control Module SCM Proof of Concept Demo - Thumbnail
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Dual Host Processor Module (HPM) and Single Secure Control Module (SCM) Proof of Concept Demo

Device Attestation over LVDS Tunneling Protocol & Interface Specification (LTPI) - Thumbnail
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Device Attestation over LVDS Tunneling Protocol & Interface Specification (LTPI)

Intel Lincoln City Reference Architecture with Lattice FPGAs-Thumbnail
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Intel Lincoln City Reference Architecture with Lattice FPGAs

IP Cores

​​eSPI Target IP Core​

IP Core

​​eSPI Target IP Core​

​​Lattice eSPI Target IP Core is compliant with the Intel eSPI specifications & has its own virtual wire channel in the user interface.​
MachXO5-NX, Mach-NX, MachXO3D, MachXO3, MachXO2 
APB, AHB-Lite, Lattice Sentry, OCP 
​​eSPI Target IP Core​
Modular Peripheral Sideband Tunneling Interface (M-PESTI) IP core

IP Core

Modular Peripheral Sideband Tunneling Interface (M-PESTI) IP core

​​The Lattice M-PESTI IP core provides early peripheral presence detection and attribute collection before system boot up.​
Certus-N2, Avant-G, Avant-X, Avant-E, MachXO5-NX, MachXO3D, MachXO3, Mach-NX 
MPESTI, UART, APB, Lattice Sentry, OCP 
Modular Peripheral Sideband Tunneling Interface (M-PESTI) IP core
DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core

IP Core

DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core

LTPI IP Core is an Open Computer Project Data Center – Secure Control Module Standards compatible solution which is introduced in the DC-SCM 2.0 Specification.
CertusPro-NX, CrossLink-NX, Certus-NX, MachXO3, MachXO3D, MachXO5-NX, Mach-NX 
CRC, LVDS, LTPI, AMBA, APB, Lattice Diamond, Lattice Radiant, Lattice Sentry, OCP 
DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core

Reference Designs

Lattice Sentry 4.0 SCM and HPM CPLD Reference Design

Reference Design

Lattice Sentry 4.0 SCM and HPM CPLD Reference Design

​​This is a CPLD design template for the Secure Control Module (SCM) and Host Platform Module (HPM) for the Sentry 4.0 Server solution platform.​
MachXO3D, MachXO5-NX 
SCM, HPM, CPLD, Lattice Sentry, Security, Defense, LTPI, MPESTI, SGPIO, eSPI, OCP 
Lattice Sentry 4.0 SCM and HPM CPLD Reference Design
MPESTI Initiator Reference Design

Reference Design

MPESTI Initiator Reference Design

MPESTI Initiator Reference Design provides the solution template which is compliant with the MPESTI Base Specification.
Avant-E, MachXO5-NX, MachXO3, MachXO3D 
MPESTI, UART, APB, AHB, RISC-V, OCP 
MPESTI Initiator Reference Design
LVDS Tunneling Protocol and Interface Reference Design

Reference Design

LVDS Tunneling Protocol and Interface Reference Design

The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.
MachXO5-NX, MachXO3D, MachXO3, Mach-NX 
CRC, LVDS, I2C, GPIO, UART, LTPI, AMBA, APB, Lattice Diamond, Lattice Propel, OCP 
LVDS Tunneling Protocol and Interface Reference Design

Documentation

Quick Reference
Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
LTPI Hardware Checklist
FPGA-TN-02417 1.0 10/7/2025 PDF 521.6 KB
LTPI Quick Start Guide
FPGA-AN-02108 1.0 10/7/2025 PDF 1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
DC-SCM LTPI IP Core – User Guide
FPGA-IPUG-02200 2.0 10/13/2025 PDF 2.1 MB
eSPI Target IP – User Guide
FPGA-IPUG-02260 1.1 12/20/2024 PDF 1.4 MB
M-PESTI Initiator IP Core – User Guide
FPGA-IPUG-02258 1.3 7/15/2025 PDF 1.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Lattice Sentry 4.0 SCM and HPM CPLD Reference Design – Source Code
9/5/2024 ZIP 86 MB
LVDS Tunneling Protocol and Interface Reference Design – Source Code
10/27/2025 ZIP 247.8 MB
LVDS Tunneling Protocol and Interface Reference Design – User Guide
FPGA-RD-02247 1.5 10/27/2025 PDF 3.5 MB
MPESTI Initiator Reference Design – Source Code
4/4/2025 ZIP 15.7 MB
MPESTI Initiator Reference Design – User Guide
FPGA-RD-02312 1.0 4/4/2025 PDF 2.9 MB
MachXO3D Lattice Sentry 4.0 SCM and HPM CPLD Reference Design – User Guide
FPGA-UG-02222 1.0 10/28/2025 PDF 4.9 MB

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