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  • PCI Express for Avant FPGAs

    IP Core

    PCI Express for Avant FPGAs

    The Lattice PCIe X8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express for Avant FPGAs
  • USB 2.0/3.2 IP Core

    IP Core

    USB 2.0/3.2 IP Core

    Lattice USB 2.0/3.2 IP Core provides a solution to interface with a USB host and can be targeted to the Lattice CrossLink-NX FPGA Devices.
    USB 2.0/3.2 IP Core
  • MPESTI Initiator Reference Design

    Reference Design

    MPESTI Initiator Reference Design

    MPESTI Initiator Reference Design provides the solution template which is compliant with the MPESTI Base Specification.
    MPESTI Initiator Reference Design
  • PCI Express for Nexus FPGAs

    IP Core

    PCI Express for Nexus FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express for Nexus FPGAs
  • APB to AHB-Lite Bridge Reference Design

    Reference Design

    APB to AHB-Lite Bridge Reference Design

    The APB to AHB-Lite Bridge Reference Design provides an interface between the low power APB and the high-speed AHB-Lite.
    APB to AHB-Lite Bridge Reference Design
  • I2C to APB Bridge Reference Design

    Reference Design

    I2C to APB Bridge Reference Design

    With support APB read / write capability, the I2C to APB Bridge Reference Design converts external I2C Master into APB Master transaction.
    I2C to APB Bridge Reference Design
  • Internal Flash Controller IP Core

    IP Core

    Internal Flash Controller IP Core

    Internal Flash Controller enables you to access the internal Flash Memory using the AHB-Lite or APB interface.
    Internal Flash Controller IP Core
  • eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)

    IP Core

    eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)

    This IP core solution uses the CL-NX FPGA’s built-in transceiver for USB 3.1 and ULPI PHY for USB 2.0. It supports SuperSpeed, High Speed and Full Speed modes.
    eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)
  • Memory Controller IP Core

    IP Core

    Memory Controller IP Core

    The Memory Controller IP reduces the effort required to integrate the LPDDR4 memory controller with the user application design.
    Memory Controller IP Core
  • RISC-V Single Core Linux (SCL) Processor

    IP Core

    RISC-V Single Core Linux (SCL) Processor

    RISC-V Single Core Linux processor includes everything required for running Linux on Lattice FPGAs and supports the RV32IMAC and RV32GC architecture.
    RISC-V Single Core Linux (SCL) Processor
  • SLVS-EC Receiver IP Core

    IP Core

    SLVS-EC Receiver IP Core

    The SLVS-EC RX IP provides the FPGA an interface to receive serial data from CMOS Image Sensors and offers a solution to convert the incoming serial data to a parallel pixel data format.
    SLVS-EC Receiver IP Core
  • SPI Flash Memory Controller IP Core

    IP Core

    SPI Flash Memory Controller IP Core

    The SPI Flash Memory Controller IP Core provides an industry-standard interface between a CPU and an off-chip SPI flash memory device.
    SPI Flash Memory Controller IP Core
  • USB 2.0 Device Controller IP Core (USB20SF)

    IP Core

    USB 2.0 Device Controller IP Core (USB20SF)

    USB20SF IP core provides FIFO interface for Data Endpoints while AHB Lite interface for Control Endpoint. This IP core supports High Speed and Full Speed modes
    USB 2.0 Device Controller IP Core (USB20SF)
  • Tri-Speed Ethernet MAC IP Core

    IP Core

    Tri-Speed Ethernet MAC IP Core

    The TSEMAC IP core have the logic, interfacing & clocking infra to ably integrate an external industry-standard Ethernet PHY with an internal processor
    Tri-Speed Ethernet MAC IP Core
  • EP550: SD / SDIO / MMC Host Controller

    IP Core

    EP550: SD / SDIO / MMC Host Controller

    Host controller for SD memory card, SDIO and MMC interface
    EP550: SD / SDIO / MMC Host Controller
  • EP560: SD / SDIO / MMC Slave Controller

    IP Core

    EP560: SD / SDIO / MMC Slave Controller

    A slave controller for SD memory card, SDIO and MMC interfaces
    EP560: SD / SDIO / MMC Slave Controller
  • AHB2AHB IP Core

    IP Core

    AHB2AHB IP Core

    The uni-directional AHB/AHB bridge is used to connect two AMBA AHB 2.0 buses clocked by synchronous clocks with any frequency ratio. The bridge is connected through a pair consisting of an AHB slave and an AHB master interface.
    AHB2AHB IP Core
  • AHB2AXIB IP Core

    IP Core

    AHB2AXIB IP Core

    This bridge allows to access an AXI3 or AXI4 slave from an AHB bus through an AHB 2.0 slave interface. The bridge has an AHB slave interface on the AHB side and AXI3 or AXI4 master interface on the AXI side.
    AHB2AXIB IP Core
  • FTMCTRL - Combined PROM/IO/SRAM/SDRAM Memory controller with EDAC IP Core

    IP Core

    FTMCTRL - Combined PROM/IO/SRAM/SDRAM Memory controller with EDAC IP Core

    Combined PROM/IO/SRAM/SDRAM Memory controller with optional EDAC. The PROM, SRAM and SDRAM areas can be EDAC-protected using a (39, 7) BCH code. The EDAC provides single error correction and double-error detection for each 32-bit memory word.
    FTMCTRL - Combined PROM/IO/SRAM/SDRAM Memory controller with EDAC IP Core
  • GR1553B Mil-Std-1553B/AS15531 Interface IP Core

    IP Core

    GR1553B Mil-Std-1553B/AS15531 Interface IP Core

    The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote Terminal (RT) or Bus Monitor (BM). The core is connected to the MIL-STD-1553B bus via a dual transceiver interface
    GR1553B Mil-Std-1553B/AS15531 Interface IP Core
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