莱迪思解决方案

IP Core

USB 2.0/3.2 IP核

莱迪思USB 2.0/3.2 IP核提供了一种连接USB主机的解决方案，适用于莱迪思CrossLink-NX FPGA最新器件。

CrossLink-NX 

USB, USB2, USB3, AHB, AHB-L, AHB-Lite, AXI, I2C, SPI, JTAG, LVDS, SLVS, FTDI 

IP Core

PCI Express for Nexus FPGAs

The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.

CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 

APB, AHB, AHB-Lite, RTL, PCI, PCIe, Bus Controllers, Defense, Automotive, PCIe Bundle, SDR 

IP Core

PCI Express for Avant and Nexus 2 FPGAs

The Lattice PCIe X8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.

Avant-G, Avant-X, Certus-N2 

AXI, AHB, AHB-Lite, RTL, PCIe, Bus Controllers, Defense, Automotive, Lattice Avant, PCI, PCIe Bundle, SDR, Avionics 

Reference Design

MPESTI Initiator Reference Design

The design specifically targets MIPI CSI-2 camera sensors and offers a flexible architecture capable of integrating multiple camera inputs based on system requirements.

Avant-E, MachXO5-NX, MachXO3, MachXO3D 

MPESTI, UART, APB, AHB, RISC-V, OCP 

Reference Design

APB to AHB-Lite Bridge Reference Design

The APB to AHB-Lite Bridge Reference Design provides an interface between the low power APB and the high-speed AHB-Lite.

MachXO3D, MachXO3, MachXO2  

APB, AHB, AMBA 

Reference Design

I2C to APB Bridge Reference Design

Support Discontinued - For Reference Only

MachXO2 , MachXO3, MachXO3D 

I2C, APB, AMBA, AHB 

IP Core

Internal Flash Controller IP Core

​​The Lattice Internal Flash Controller for MachXO5-NX IP Core has a system bus interface to access the registers.​

MachXO5-NX 

AHB, AHB-Lite, Security, Automotive, Flash 

IP Core

Memory Controller IP Core

The Memory Controller IP reduces the effort required to integrate the LPDDR4 memory controller with the user application design.

CertusPro-NX, Avant-E, Avant-G, Avant-X, MachXO5-NX, Certus-N2 

LPDDR4, DDR SDRAM, APB, AHB, Memory Controller, Automotive, Memory Controller Bundle, Lattice Drive, Avionics 

IP Core

RISC-V Single Core Linux (SCL) Processor

RISC-V Single Core Linux processor includes everything required for running Linux on Lattice FPGAs and supports the RV32IMAC and RV32GC architecture.

CertusPro-NX 

RISC-V, Soft Processor, DDR Memories, AHB, AHB-Lite, AMBA, AXI, GPIO Control, UART 

IP Core

SLVS-EC Receiver IP Core

The SLVS-EC RX IP provides the FPGA an interface to receive serial data from CMOS Image Sensors and offers a solution to convert the incoming serial data to a parallel pixel data format.

CertusPro-NX 

SLVS-EC, APB, AHB, AMBA, PMA, PCS, MPCS 

IP Core

SPI Flash Memory Controller IP Core

The SPI Flash Memory Controller IP Core provides an industry-standard interface between a CPU and an off-chip SPI flash memory device.

CertusPro-NX, Certus-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X, MachXO5-NX 

SPI, SPI Flash, AHB-Lite, AHB, APB, Memory Controller, Automotive 

IP Core

USB 2.0 Device Controller IP Core (USB20SF)

USB20SF IP core provides FIFO interface for Data Endpoints while AHB Lite interface for Control Endpoint. This IP core supports High Speed and Full Speed modes

CrossLink-NX, CertusPro-NX 

ARM, RISC-V, Soft Processor, FMC, AHB, AHB-Lite, AXI, Camera, ULPI, USB2 

IP Core

​​USB 3.2 Gen 1 Device Controller IP Core (USB32SF)​

This IP core solution uses the FPGA’s built-in transceiver for USB 3.2 and ULPI PHY for USB 2.0. It supports SuperSpeed, High Speed and Full Speed modes.

CrossLink-NX, CertusPro-NX 

ARM, RISC-V, Soft Processor, FMC, AHB, AHB-Lite, AXI, USB Type-C, USB3, Camera, Image Processing, MIPI 

IP Core

三倍速以太网MAC

在主机处理器和以太网之间发送和接收数据。符合IEEE 802.3标准。支持10/100/1000 Mbps传输速率。

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, LatticeSC/M, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E, Avant-G, Avant-X, Certus-N2 

Data Communication, Ethernet, Defense, Automotive, APB, AXI, AXI-Lite Interface, AHB, Ethernet Bundle 

IP Core

EP550: SD / SDIO / MMC 主控制器

Host controller for SD memory card, SDIO and MMC interface

LatticeXP2, LatticeSC/M 

AHB, SD Memory 

IP Core

EP560: SD / SDIO / MMC 从控制器

A slave controller for SD memory card, SDIO and MMC interfaces

LatticeECP2/M, LatticeXP2, LatticeSC/M 

AHB, SD Memory 

IP Core

AHB2AHB IP Core

The uni-directional AHB/AHB bridge is used to connect two AMBA AHB 2.0 buses clocked by synchronous clocks with any frequency ratio. The bridge is connected through a pair consisting of an AHB slave and an AHB master interface.

CertusPro-NX, Certus-NX 

AHB, AMBA 

IP Core

AHB2AXIB IP Core

This bridge allows to access an AXI3 or AXI4 slave from an AHB bus through an AHB 2.0 slave interface. The bridge has an AHB slave interface on the AHB side and AXI3 or AXI4 master interface on the AXI side.

CertusPro-NX, Certus-NX 

AHB, AMBA, AXI 

IP Core

FTMCTRL - Combined PROM/IO/SRAM/SDRAM Memory controller with EDAC IP Core

Combined PROM/IO/SRAM/SDRAM Memory controller with optional EDAC. The PROM, SRAM and SDRAM areas can be EDAC-protected using a (39, 7) BCH code. The EDAC provides single error correction and double-error detection for each 32-bit memory word.

CertusPro-NX, CrossLink-NX, Certus-NX 

SDRAM, AHB 

IP Core

GR1553B Mil-Std-1553B/AS15531 Interface IP Core

The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote Terminal (RT) or Bus Monitor (BM). The core is connected to the MIL-STD-1553B bus via a dual transceiver interface

CertusPro-NX, Certus-NX 

AHB, AMBA, Bus Controllers