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  • USB 2.0/3.2 IP Core

    IP Core

    USB 2.0/3.2 IP Core

    Lattice USB 2.0/3.2 IP Core provides a solution to interface with a USB host and can be targeted to the Lattice CrossLink-NX FPGA Devices.
    CrossLink-NX 
    USB, USB2, USB3, AHB, AHB-L, AHB-Lite, AXI, I2C, SPI, JTAG, LVDS, SLVS, FTDI 
    USB 2.0/3.2 IP Core
  • MPESTI Initiator Reference Design

    Reference Design

    MPESTI Initiator Reference Design

    MPESTI Initiator Reference Design provides the solution template which is compliant with the MPESTI Base Specification.
    Avant-E, MachXO5-NX, MachXO3, MachXO3D 
    MPESTI, UART, APB, AHB 
    MPESTI Initiator Reference Design
  • PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    IP Core

    PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 
    APB, AHB, AHB-Lite, RTL, PCI, PCIe, Bus Controllers, Defense, Automotive 
    PCI Express x1 & x4 IP Core for Nexus-based FPGAs
  • APB to AHB-Lite Bridge Reference Design

    Reference Design

    APB to AHB-Lite Bridge Reference Design

    The APB to AHB-Lite Bridge Reference Design provides an interface between the low power APB and the high-speed AHB-Lite.
    MachXO3D, MachXO3, MachXO2 
    APB, AHB, AMBA 
    APB to AHB-Lite Bridge Reference Design
  • I2C to APB Bridge Reference Design

    Reference Design

    I2C to APB Bridge Reference Design

    With support APB read / write capability, the I2C to APB Bridge Reference Design converts external I2C Master into APB Master transaction.
    MachXO2, MachXO3, MachXO3D 
    I2C, APB, AMBA, AHB 
    I2C to APB Bridge Reference Design
  • Internal Flash Controller IP Core

    IP Core

    Internal Flash Controller IP Core

    Internal Flash Controller enables you to access the internal Flash Memory using the AHB-Lite or APB interface.
    MachXO5-NX 
    AHB, AHB-Lite, Security, Automotive, Flash 
    Internal Flash Controller IP Core
  • eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)

    IP Core

    eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)

    This IP core solution uses the CL-NX FPGA’s built-in transceiver for USB 3.1 and ULPI PHY for USB 2.0. It supports SuperSpeed, High Speed and Full Speed modes.
    CrossLink-NX 
    ARM, RISC-V, Soft Processor, FMC, AHB, AHB-Lite, AXI, USB Type-C, USB3, USB2, ULPI 
    eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)
  • Memory Controller IP Core

    IP Core

    Memory Controller IP Core

    The Memory Controller IP reduces the effort required to integrate the LPDDR4 memory controller with the user application design.
    CertusPro-NX, Avant-E 
    LPDDR4, DDR SDRAM, APB, AHB, Memory Controller, Automotive 
    Memory Controller IP Core
  • RISC-V Single Core Linux (SCL) Processor

    IP Core

    RISC-V Single Core Linux (SCL) Processor

    RISC-V Single Core Linux processor includes everything required for running Linux on Lattice FPGAs and supports the RV32IMAC and RV32GC architecture.
    CertusPro-NX 
    RISC-V, Soft Processor, DDR Memories, AHB, AHB-Lite, AMBA, AXI, GPIO Control, UART 
    RISC-V Single Core Linux (SCL) Processor
  • SLVS-EC Receiver IP Core

    IP Core

    SLVS-EC Receiver IP Core

    The SLVS-EC RX IP provides the FPGA an interface to receive serial data from CMOS Image Sensors and offers a solution to convert the incoming serial data to a parallel pixel data format.
    CertusPro-NX 
    SLVS-EC, APB, AHB, AMBA, PMA, PCS, MPCS 
    SLVS-EC Receiver IP Core
  • SPI Flash Memory Controller IP Core

    IP Core

    SPI Flash Memory Controller IP Core

    The SPI Flash Memory Controller IP Core provides an industry-standard interface between a CPU and an off-chip SPI flash memory device.
    Avant-E, CertusPro-NX, Certus-NX, CrossLink-NX 
    SPI, SPI Flash, AHB-Lite, AHB, APB, Memory Controller, Automotive 
    SPI Flash Memory Controller IP Core
  • USB 2.0 Device Controller IP Core (USB20SF)

    IP Core

    USB 2.0 Device Controller IP Core (USB20SF)

    USB20SF IP core provides FIFO interface for Data Endpoints while AHB Lite interface for Control Endpoint. This IP core supports High Speed and Full Speed modes
    CrossLink-NX 
    ARM, RISC-V, Soft Processor, FMC, AHB, AHB-Lite, AXI, Camera, ULPI, USB2 
    USB 2.0 Device Controller IP Core (USB20SF)
  • Tri-Speed Ethernet MAC IP Core

    IP Core

    Tri-Speed Ethernet MAC IP Core

    The TSEMAC IP core have the logic, interfacing & clocking infra to ably integrate an external industry-standard Ethernet PHY with an internal processor
    ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, LatticeSC/M, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E 
    Connectivity IP Suite, Data Communication, Ethernet, Value IP Suite, Defense, Automotive, APB, AXI, AXI-Lite Interface, AHB 
    Tri-Speed Ethernet MAC IP Core
  • EP550: SD / SDIO / MMC Host Controller

    IP Core

    EP550: SD / SDIO / MMC Host Controller

    Host controller for SD memory card, SDIO and MMC interface
    LatticeXP2, LatticeSC/M 
    AHB, SD Memory 
    EP550: SD / SDIO / MMC Host Controller
  • EP560: SD / SDIO / MMC Slave Controller

    IP Core

    EP560: SD / SDIO / MMC Slave Controller

    A slave controller for SD memory card, SDIO and MMC interfaces
    LatticeECP2/M, LatticeXP2, LatticeSC/M 
    AHB, SD Memory 
    EP560: SD / SDIO / MMC Slave Controller
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