Internal Flash Controller IP Core

Related Products

The Internal Flash Controller for MachXO5™-NX enables you to access the internal Flash Memory of MachXO5-NX using the AHB-Lite or APB interface. This IP also has four sub-blocks: Register Block, Data Buffer, Controller, and Flash Memory.

Block Partitioning - Flash memory of LFMXO5 can modify the partition sizes by changing the attributes prior to IP generation.

Features

  • AHB-Lite interface
  • APB interface
  • Initial user data to be programmed into the Flash Memory
  • Up to 133 MHz input clock frequency
  • Only supported in LFMXO5 devices

Block Diagram

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
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Internal Flash Controller IP Core - User Guide
FPGA-IPUG-02174 1.1 5/31/2022 PDF 1.4 MB

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