Unmanned Aerial Vehicles (UAVs)

Low power innovations for the next frontier of aviation

Related Applications

During the last 25 years, defense-grade unmanned aerial vehicles have benefitted from Lattice's advances in vision processing and sensor fusion to solve complex national security challenges. In the coming years, advances in process technology, algorithms and machine learning will deliver a new set of robust capabilities and use cases while advancing flight control and autonomy, lowering mission costs and extending the payload and duration of missions.

Focused on vision processing performance at the lowest power and always-on AI built on highly reliable FD-SOI platform, Lattice delivers industry leading solutions to help develop next generation avionics with reduced risk and time to market.

Key Lattice FPGA Features & Benefits

  • Best-in-class performance for vision processing and video bridging applications with up to 75% lower power vs similar FPGAs
  • Small form factor packaging with sizes as small as 4 mm x 4 mm
  • Built-in high-speed connectivity including embedded MIPI DPHY, PCIE, DDR3, 1.5 Gbps LVDS and integrated Analog-to-Digital converters simplify data acquisition and processing, sensor fusion, RF front-end interfaces, and control plane implementations
  • Lowest power, parallel multi-sensor interfaces for sensor fusion and low latency networking solutions help integrate real time data to provide a single, autonomous operating picture and enable more informed decisions

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Example Applications

Image Sensor Processing

  • Bridge one or multiple CSI-2 image sensors to processor interface (PCIe, CMOS, CSI-2)
  • Integrate full functional universal video pipeline
  • Examples: Debayer, color correction matrix, RGB gain, gamma correction…
  • Offloads ISP functionality from the processor

Sensor Aggregation

  • Aggregate up to 11 MIPI CSI-2 image sensors into one MIPI CSI-2 output
  • Stitch data together into larger horizontal video frame
  • Use external DDR memory to stitch data into larger vertical video frame
  • Arbitrate data from image sensors using unique virtual channel numbers
  • Extend limited processor sensor interface capability and connect more sensors

Co-processing

  • Off-load CPU by using Certus-NX as a co-processor to accelerate complex functions
  • DDR3 & LPDDR2 interface support (up to 1066 Mbps) and on-chip embedded memory (up to 2.9 Mbit) provide multiple options for data buffering
  • Compact packages as small as 6x6 mm with PCIe and DDR memory interface support

Reference Designs

Human Face Identification Reference Design

Reference Design

Human Face Identification Reference Design

Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
Human Face Identification Reference Design
1 to N MIPI CSI-2/DSI Duplicator Reference Design

Reference Design

PDM Microphone Aggregation

Reference Design

PDM Microphone Aggregation

Aggregate up to 8 PDM microphones and connection to a processor over I2S or SPI with no impact in audio quality. Ideal for beam-forming. PCM output at 48HKz.
PDM Microphone Aggregation
Infrared Remote Tx/Rx Reference Designs

Reference Design

Infrared Remote Tx/Rx Reference Designs

Implements an interface to IR receive and/or IR transmit. This includes PWM (pulse width modulation) timing and protocol conversion to an SPI /I2C bus
Infrared Remote Tx/Rx Reference Designs
LED/OLED Driver Reference Design

Reference Design

LED/OLED Driver Reference Design

Drive an LED via WISHBONE bus. Default is targeted to a GM1WA55311A LED but can be used to control other LEDs or OLEDs with similar functions.
LED/OLED Driver Reference Design

IP Cores

CNN Plus Accelerator IP Core

IP Core

CNN Plus Accelerator IP Core

CNN Plus IP is a flexible accelerator IP that simplifies implementation of Ultra-Low power AI by leveraging capabilities of Lattice FPGAs.
CNN Plus Accelerator IP Core
Convolutional Neural Network (CNN) Compact Accelerator

IP Core

Convolutional Neural Network (CNN) Compact Accelerator

Implement AI solutions with CNNs or BNNs that have power consumption in the mW range. Works with Lattice Neural Network Compiler software tool.
Convolutional Neural Network (CNN) Compact Accelerator
CNN Co-Processor Accelerator IP

IP Core

CNN Co-Processor Accelerator IP

A CNN co-processor accelerator engine for use with low power Lattice FPGAs. The engine can be used with a RISC-V processor to create an SOC and implement TF Lite-based acceleration applications that leverage the parallel compute and distributed resource capabilities of Lattice FPGAs.
CNN Co-Processor Accelerator IP
Color Space Converter (CSC) IP Core

IP Core

Color Space Converter (CSC) IP Core

The Lattice Color Space Converter IP Core is widely parameterizable and can support any custom color space conversion requirement.
Color Space Converter (CSC) IP Core
Gamma Corrector IP Core

IP Core

Gamma Corrector IP Core

The Lattice Gamma Corrector IP core is a multi-color plane gamma correction system that can support almost any custom gamma correction requirement.
Gamma Corrector IP Core

Development Kits & Boards

Embedded Vision Development Kit

Board

Embedded Vision Development Kit

Three-board Video Interface Platform (VIP) modular kit. Includes 2 MIPI/D-PHY camera input, FPGA processing, HDMI output. More Input/Output boards available.
Embedded Vision Development Kit
Lattice Sentry Demo Board for MachXO3D

Board

Lattice Sentry Demo Board for MachXO3D

A complete platform to help you develop and test a NIST 800-193-compliant PFR solution. Includes numerous features to enable debug, interface and expansion
Lattice Sentry Demo Board for MachXO3D
Certus-NX Versa Evaluation Board

Board

Certus-NX Versa Evaluation Board

The Certus-NX Versa Evaluation Board enables designers with connectivity features of the Certus-NX FPGA and assist engineers with prototyping and testing.
Certus-NX Versa Evaluation Board
Lattice Sentry Demo Board for Mach-NX

Board

Lattice Sentry Demo Board for Mach-NX

A complete platform to help you develop and test a NIST 800-193-compliant PFR solution. Includes numerous features to enable debug, interface and expansion
Lattice Sentry Demo Board for Mach-NX
HM01B0 UPduino Shield

Board

HM01B0 UPduino Shield

A complete development kit for implementing Artificial Intelligence (AI) using vision and sound as sensory inputs to a low-cost, low-power iCE40 UltraPlus FPGA.
HM01B0 UPduino Shield

Demos

PCIe Basic Demo for Lattice Nexus-based FPGAs

Demo

PCIe Basic Demo for Lattice Nexus-based FPGAs

The PCIe Basic Demo allows you to control three 7 segment LEDs and manipulate the onboard memory of the FPGA through the PCIe slot.
PCIe Basic Demo for Lattice Nexus-based FPGAs
PCIe Colorbar Demo for Lattice Nexus-based FPGAs

Demo

PCIe Colorbar Demo for Lattice Nexus-based FPGAs

PCIe Colorbar Demo displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.
PCIe Colorbar Demo for Lattice Nexus-based FPGAs
PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

Demo

PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.
PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs
PCIe Multifunction Demo for Lattice Nexus-based FPGAs

Demo

PCIe Multifunction Demo for Lattice Nexus-based FPGAs

Demonstrates the multifunction capabilities of the Crosslink-NX FPGA that allows access to GPIO, MDIO and I2C registers.
PCIe Multifunction Demo for Lattice Nexus-based FPGAs
Human Presence Detection AI Demo

Demo

Human Presence Detection AI Demo

Uses an artificial intelligence (AI) algorithm to detect human presence with either the powerful ECP5 FPGA, or small, low-power iCE40 UltraPlus FPGA.
Human Presence Detection AI Demo

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 2.1 7/18/2024 PDF 614.6 KB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 2.1 11/20/2024 PDF 1.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 2.1 7/18/2024 PDF 614.6 KB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 2.1 11/20/2024 PDF 1.1 MB

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