Lattice Solutions

Everything you need to quickly and easily complete your design

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Providers
  • Embedded Vision Development Kit

    Board

    Embedded Vision Development Kit

    Three-board Video Interface Platform (VIP) modular kit. Includes 2 MIPI/D-PHY camera input, FPGA processing, HDMI output. More Input/Output boards available.
    Embedded Vision Development Kit
  • MIPI CSI-2 Virtual Channel Aggregation

    Reference Design

  • N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

    Reference Design

  • Single Wire Aggregation

    Reference Design

    Single Wire Aggregation

    Use a low-cost FPGA to aggregate multiple data streams such as I2C, UART, I2S and GPIO in TDM fashion, transmit a over single wire, and de-aggregate.
    Single Wire Aggregation
  • Single Wire Aggregation Demo / Development Board

    Board

    Single Wire Aggregation Demo / Development Board

    Use the world’s smallest form factor FPGAs to aggregate multiple data streams such as I2C, I2S and GPIO in TDM fashion, transmit over single wire, and de-aggregate.
  • 8 to 1 Microphone Aggregator Board

    Board

    8 to 1 Microphone Aggregator Board

    Daughter board for iCE40 UltraPlus Mobile Development Platform (MDP) for aggregation of up to eight PDM I2S microphones.
    8 to 1 Microphone Aggregator Board
  • PDM Microphone Aggregation

    Reference Design

    PDM Microphone Aggregation

    Aggregate up to 8 PDM microphones and connection to a processor over I2S or SPI with no impact in audio quality. Ideal for beam-forming. PCM output at 48HKz.
    PDM Microphone Aggregation
  • Sensor Data Buffer

    Reference Design

    Sensor Data Buffer

    Interfaces between multiple I2C-based sensors and a processor's UART. Saves power and resources by always collecting data, while the processor sleeps.
    Sensor Data Buffer
  • Sensor Interfacing and Preprocessing

    Reference Design

    Sensor Interfacing and Preprocessing

    Aggregates data from multiple I2C interfaces and performs preprocessing like buffering, timestamping and complex event triggering based on data analysis.
    Sensor Interfacing and Preprocessing
  • LPC (Low Pin Count) Bus Controller

    Reference Design

    LPC (Low Pin Count) Bus Controller

    Implements a Low Pin Count bus controller - based on the Intel Low Pin Count Interface Specification (version 1.1)
    LPC (Low Pin Count) Bus Controller
  • SPI GPIO Expander

    Reference Design

    SPI GPIO Expander

    Expand microprocessor general purpose I/O ports with a Serial Peripheral Interface (SPI)
    SPI GPIO Expander
  • GPIO Expander

    Reference Design

    GPIO Expander

    Provides a solution that uses a Lattice PLD as a GPIO Expander
    GPIO Expander
  • 7:1 LVDS Video Interface

    Reference Design

    7:1 LVDS Video Interface

    Implements standard 7:1 LVDS interfaces using the FPGA I/O structure
    7:1 LVDS Video Interface
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