| Tested Devices* |
Language |
Performance |
I/O Pins |
Design Size |
Revision |
| LCMXO640C-3T100C |
Verilog/VHDL |
>100 MHz |
47 |
238/206 LUTs |
1.2 |
| LC4256ZE-5TN100C |
Verilog/VHDL |
>100 MHz |
47 |
187/194 Macrocells |
1.2 |
| LFE3-17EA-6FTN256C |
Verilog/VHDL |
> 100 MHz |
47 |
242/211 LUTs |
1.3 |
| LFXP2-5E-5TN144C |
Verilog/VHDL |
>100 MHz |
47 |
277/274 LUTs |
1.3 |
| LPTM10-12107-3FTG208CES |
Verilog/VHDL |
>100 MHz |
47 |
250/207 LUTs |
1.2 |
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.