Lattice Radiant Software

Windows

The Lattice Radiant Software Base executable contains all of the design tools and features for you to use Lattice FPGAs from design entry to bitstream download. The supported Windows Operating Systems are Windows 7 64-bit, Windows 8/8.1 64-bit and Windows 10 64-bit.

Linux

The Lattice Radiant Software Base executable contains all of the design tools and features for you to use Lattice FPGAs from design entry to bitstream download. The supported Linux Operating Systems are Red Hat Enterprise Linux 6.6 or 7 64-bit and Ubuntu 16.04 LTS 64-bit.

Currently, Lattice Radiant Design Software only requires a Free License.

Read Licensing FAQ

• Unified FPGA Design Framework – Contains unified design database, timing constraint and analysis engine to drive predictable FPGA design convergence.
• New GUI – Redesigned GUI provides simple, intuitive and effective user operations with a modern look and feel.
• Unified GUI Operation – Redesigned GUI provides unified zoom/select/pan GUI operations across all Lattice Radiant tools for consistent and efficient GUI operations.
• Integrated tools sets - Ease of design navigation and debugging enabled by integration of major tools such as Netlist View to Device Constraint Editor, Floorplan View and Physical View.
• Process Toolbar – New process toolbar GUI to control and streamline user design implementation steps for execution of “Synthesis Design,” “MAP Design,” “Place & Route Design” and “Export Files,” along with effective presentations of the implementation report.
• Industry Standard Support – Support of Industry Standard IEEE1735 IP Encryption and Synopsys Design Constraint (SDC) for maximum interoperability.
• Source Editor – HDL source code editing that includes keyword highlight support for VHDL, Verilog HDL, SDC and Lattice constraint attributes.
• IP Catalog – an integrated interface to Lattice catalog of intellectual property (IP) optimized for Lattice programmable products.
• Lattice Synthesis Engine (LSE) – Lattice developed logic-synthesis tool designed specifically to produce the best possible results for ultra-low density and low density FPGAs.
• Netlist Analyzer – An integrated pre- and post- synthesis result viewing and cross probing GUI.
• Cross Probing – Comprehensive, new close-looped physical to logical design implementation cross probing.
• Message Console – New common message viewing window console with effective classification and filtering capabilities.
• Device Constraint Editor – Integrates netlist, package, device windows as well as constraint management spreadsheet to provide a common physical device constraint adding, editing and viewing.
  • Spreadsheet window: To enter and view design constraints such as pin assignments, clock resource usage, global constraints and more.
  • Package window: GUI based assignment of signals to pins.
  • Device window: To provide the ability to browse device specific resources and cross-probe to other views.
  • Netlist window: To provide browsing of design ports/pins, and nets for drag and dropping into other views for constraints settings.
• Timing Constraint Editor – An integrated GUI to allow users to enter and view design constraints such as clock, global constraints, timing constraints and more.
• Floorplan View – A tool to view design and edit placement group constraints.
• Physical View – A tool to view detailed physical routing paths for more in depth understanding of timing issues.
• Multiple Implementations – Enables multiple seeds to allow multiple versions of a design within a single project for easy design explorations.
• Multiple Strategies – Enables implementation “recipes” to be applied to any implementation within a project or shared between projects.
• Power Calculator – Enables accurate data driven power calculation and estimation based on silicon performance data, and to provide graphical power displays and reports.
• Reveal Inserter – Enables a signal-centric model that allows easy insertion of embedded logic analyzer debug hardware for real-time analysis.
• Reveal Analyzer – Provides the ability to use multi-event triggering, which can be dynamically changed at run-time and an integrated waveform for displaying captured events from the target FPGA.
• Radiant Programmer – Available within Lattice Radiant software and as a standalone tool, Radiant Programmer allows easy direct normal programming of single or multiple FPGA devices.
• Radiant Deployment Tool – Provides an intuitive wizard approach to create the appropriate device programming file in the format required by your deployment method.
• Tcl Scripting – For flow automation and script control instead of GUI.
• Radiant Simulation Wizard – A tool to guide you through all the necessary steps to get your design to a simulator in the format you want.
• Third Party Tools – Synopsys SynplifyPro and Aldec Active-HDL Lattice Edition II