Hitless Updates

Background Update and Reconfigure with Zero Downtime

In mission critical systems such as data center, storage or networking equipment, feature improvements and bug fixes are performed through background updates. However, up to now, designers have been avoiding updating of the control Programmable Logic Device (which typically performs functions such as power management, reset management, glue logic and other housekeeping functions on the board) as it forced a power cycle or reset of the entire system to enable the new algorithm to take effect.

The Lattice Semiconductor MachXO3™ device, the most popular control PLD, can be updated in the background and the new algorithm takes effect without interrupting board-level operations. There is no need for a power-cycle or reset of the device or the system. This feature is known as the hitless or zero-downtime system update.

Transparent Background Programming – Update MachXO3LF configuration Flash memory with zero downtime and no interruption to the active configuration.

Hitless I/O During Reconfiguration – New program refresh without power cycling and glitches to the active configuration.

Reliability with Dual Boot Support – Automatic recovery to golden failsafe image protects system during reprogramming.

Features

  • Background program over SPI, I2C or JTAG
  • Freeze I/O during reconfiguration
  • Start state machines from defined state based on Frozen I/O
  • Dual boot from golden image in external SPI Flash
  • In-field update with high reliability and zero downtime

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Documentation

Quick Reference
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-02198 4.4 10/17/2023 PDF 1.4 MB
MachXO3 Programming and Configuration User Guide
FPGA-TN-02055 2.9 3/31/2023 PDF 1.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-02198 4.4 10/17/2023 PDF 1.4 MB
MachXO3 Programming and Configuration User Guide
FPGA-TN-02055 2.9 3/31/2023 PDF 1.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
MachXO3D Hitless I/O and Hitless EBR Demo
FPGA-UG-02069 1.1 8/13/2020 PDF 3 MB
MachXO3LF 9400C Hitless I/O Demo User Guide
FPGA-UG-02022 1.0 6/28/2017 PDF 1.5 MB
Hitless Update Demo User Guide
UG118 1.0 6/16/2016 PDF 1.9 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
MachXO3LF 9400C Hitless I/O Demo
1.0 6/28/2017 ZIP 1.4 MB
MachXO3D Hitless I/O and Hitless EBR Demo
1.1 8/13/2020 ZIP 3 MB
MachXO3 Hitless Update Demo
1.0 6/16/2016 ZIP 1.9 MB

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