Hitless Updates

Background Update and Reconfigure with Zero Downtime

Transparent Background Programming – Update MachXO3LF configuration Flash memory with zero downtime and no interruption to the active configuration.

Hitless I/O During Reconfiguration – New program refresh without power cycling and glitches to the active configuration.

Reliability with Dual Boot Support – Automatic recovery to golden failsafe image protects system during reprogramming.

Features

  • Background program over SPI, I2C or JTAG
  • Freeze I/O during reconfiguration
  • Start state machines from defined state based on Frozen I/O
  • Dual boot from golden image in external SPI Flash
  • In-field update with high reliability and zero downtime

Block Diagram

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
MachXO3 Programming and Configuration User Guide
FPGA-TN-02055 2.7 12/21/2021 PDF 1.9 MB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-02198 4.1 6/16/2022 PDF 1.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
MachXO3 Programming and Configuration User Guide
FPGA-TN-02055 2.7 12/21/2021 PDF 1.9 MB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-02198 4.1 6/16/2022 PDF 1.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
MachXO2 and MachXO3 Starter Kit Evaluation Board User Guide
FPGA-EB-02036 1.4 1/31/2022 PDF 1.8 MB
Hitless Update Demo User Guide
UG118 1.0 6/16/2016 PDF 1.9 MB

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