MachXO3D – Secure FPGA Enabling Hardware Root-of-Trust

Enhance Secure Control Applications with Hardware Root-of-Trust and Dual Boot Capabilities

Builds on Proven MachXO3 Architecture – MachXO3D adds an immutable embedded security block, enhanced control functions, expanded user flash memory up to 2700 kbits, and available in Commercial, Industrial and AEC-Q100 qualified Automotive grade.

Highly Secured FPGA – Immutable security enables Hardware Root-of-Trust and pre-verified cryptographic functions such as ECDSA, ECIES, AES, SHA, HMAC, TRNG, Unique Secure ID and Public/Private Key Generation.

On Device Dual Boot Flash – No need for external memory for dual boot configuration. On device dual boot flash enables fail-safe programming and provides flexible in-field updates.

Features

  • Simplifies implementation of hardware security by integrating Root-of-Trust in your platform’s first on, last off device
  • Supports security throughout the product lifecycle including device manufacturing and transport, platform manufacturing, installation, operation and decommissioning
  • Enables comprehensive protection against a variety of threats by providing data security, equipment security, data authentication, design security and brand protection
  • Programmable logic combined with secure dual boot configuration block provides flexibility during design implementation and enables secure updates after equipment deployment
  • Delivers robust security and pre-verified cryptographic functions compliant with NIST SP 800-193 PFR and CAVP guidelines to protect non-volatile memory, detect malicious code, and recover in case of corruption

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Security

MachXO3D is NIST-CAVP certified and complies with NIST SP 800-193 PFR Guidelines

Lattice has completed the National Institute of Standards and Technology (NIST) Cryptographic Algorithm Validation Program (CAVP) certification for the MachXO3D™ cryptographic functions listed below. NIST CAVP provides validation testing of FIPS-approved and NIST-recommended cryptographic algorithms and their individual components. Federal Information Processing Standards (FIPS) is the U.S. federal government’s standard for cryptographic software.

The MachXO3D establishes a hardware Root-of-Trust (ROT) to protect, detect and recover the device and other components from unauthorized firmware access throughout their systems’ lifecycle, from the point of manufacturing to end of life. These security functions are compliant with NIST SP 800-193 PFR guidelines and now certified with NIST-CAVP validation tests described in below table.

NIST-CAVP Certifications for MachXO3D™ cryptographic functions

Validation Number C998
Test Capabilities Description
AES-ECB Direction: Decrypt, Encrypt
Key Length: 128, 256
ECDSA KeyGen (186-4) Curve: P-256
Secret Generation Mode: Testing Candidates
ECDSA SigGen (186-4) Capabilities:
    Curve: P-256
    Hash Algorithm: SHA2-256
ECDSA SigVer (186-4) Capabilities:
    Curve: P-256
    Hash Algorithm: SHA2-256
HMAC DRBG Prediction Resistance: No
Capabilities:
Mode: SHA2-256
Entropy Input: 256
Nonce: 256
Personalization String Length: 0
Additional Input: 0
Returned Bits: 256
HAC-SHA2-256 MAC: 256
Key sizes < block size
KAS-ECC Function: Key Pair Generation
KAS-ECC CDH-Component Function: Key Pair Generation
SHA-256 Message Length: 8-65536 Increment 8

To see this certification on the NIST website, click here.

To learn more about NIST CAVP, click here.

Family Table

MachXO3D Device Selection Guide
Features MachXO3D-4300 MachXO3D-9400
LUTs 4300 9400
Distributed RAM (kbits) 34 73
EBR SRAM (kbits) 92 432
UFM (kbits) 367/11223 1088/26933
PLLs 2 2
Hardened Security Block 1 1
Oscillator 1 1
On-chip Dual-boot Yes Yes
I3C compatible I/O Yes1 Yes1
MIPI D-PHY Support2 Yes Yes
VCC - 2.5/3.3V HC / ZC 5 HC / ZC 5
VCC - 1.2V4 -
HE
Temperature Grades C / I / A6 C / I / A6

1. 4 pairs of I/O in bank 3 with I3C dynamic pull up capability.
2. HC device only.
3. When dual-boot is disabled, image space can be repurposed as extra UFM.
4. Available in automotive grade only
5. HC = High Performance / ZC = Low Power Option
6. C = Commercial, I = Industrial, A = Automotive

0.5 mm Spacing I/O Count

MachXO3D-4300 MachXO3D-9400
72 QFN (10 mm x 10 mm) 58 (HC, ZC) 58 (HC, ZC)
0.8 mm Spacing I/O Count

MachXO3D-4300 MachXO3D-9400
256-ball caBGA (14 mm x 14 mm) 206 (HC1, ZC) 206 (HC, ZC1, HE2)
400-ball caBGA (17 mm x 17 mm)
335 (HC, ZC)
484-ball caBGA (19 mm x 19 mm)
383 (ZC1, HE2)

1. Available in automotive grade
2. Available in automotive grade only

Example Solutions

Secure Control PLD

  • Enhances Secure Control PLD functionality with dual boot and hardware root-of-trust to simplify implementation of comprehensive, flexible and robust hardware security throughout product lifecycle.

Secure Server

  • Hardened secure configuration block enables MachXO3D to protect, detect and recover itself from malicious attacks
  • FPGA fabric enables parallel processing capability to protect, detect and recover multiple platform firmware at the same time
  • Compliant with NIST SP 800 193 Platform Firmware Resiliency (PFR) guidelines

Chain of Trust Implementation

  • Hardware Root-of-Trust is the first link in chain of trust that protects entire systems
  • Hardened device configuration engine cryptographically authenticates MachXO3D’s configuration image at power-on
  • Embedded security block provides cryptographic functions to authenticate other platform firmware at power-on
  • With instant-on capability MachXO3D is the first device to boot up securely on the platform and as such is an excellent anchor for Chain of Trust

Battery Management Control using MachXO3D

  • MachXO3D provides controller for the battery management for mobile and portable embedded systems
  • Intelligent cell balancing for charge equalization for each battery cell.
  • Control charge/ discharge process and receive real-time battery information like State of Charge (SOC) and State of Health (SOH)

Design Resources

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Application Notes

Learn how to get the most from our line-up of FPGAs / development boards

Software

Complete Design Flows, High Ease of Use

Development Kits & Boards

Our development boards & kits help streamline your design process

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
MachXO3D Soft Error Detection (SED)/Correction (SEC) Usage Guide
FPGA-TN-02124 0.90 5/21/2019 PDF 1.1 MB
MachXO3D Programming and Configuration Usage Guide
FPGA-TN-02069 0.9 5/21/2019 PDF 1.7 MB
MachXO3D sysCLOCK PLL Usage Guide
FPGA-TN-02070 0.90 6/16/2019 PDF 1.8 MB
MachXO3D sysI/O Usage Guide
FPGA-TN-02068 0.90 6/16/2019 PDF 1.1 MB
Using Hardened Control Functions in MachXO3D Devices Reference Guide
FPGA-TN-02119 0.90 8/5/2019 PDF 2.2 MB
Power Decoupling and Bypass Filtering for Programmable Devices
TN1068 1.0 5/1/2004 PDF 31.4 KB
MachXO3D 256-Pin caBGA Package Migration File
1.0 5/21/2019 CSV 15 KB
MachXO3D-9400 Pinout
1.0 5/21/2019 CSV 28.1 KB
MachXO3D 72-Pin QFN Package Migration File
1.0 5/21/2019 CSV 4.7 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 4.1 5/20/2019 PDF 4.6 MB
Using Hardened Control Functions in MachXO3D Devices
FPGA-TN-02117 0.91 7/24/2020 PDF 1.7 MB
Implementing High-Speed Interfaces with MachXO3D Usage Guide
FPGA-TN-02065 1.0 7/28/2020 PDF 2.1 MB
Memory Usage Guide for MachXO3D Devices
FPGA-TN-02066 1.0 7/24/2020 PDF 4.6 MB
MachXO3D Hardware Checklist
FPGA-TN-02104 1.0 7/24/2020 PDF 782.2 KB
MachXO3D-4300 Pinout
1.02 6/1/2020 CSV 17.5 KB
MachXO3D Family Data Sheet
FPGA-DS-02026 1.1 9/16/2020 PDF 8.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
MachXO3D Family Data Sheet
FPGA-DS-02026 1.1 9/16/2020 PDF 8.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
MachXO3D Embedded Security Block
This document would be provided through Technical Support Request after sign-in to Lattice web site. Please refer to Answer Database FAQ 5781 for detail instruction.
FPGA-TN-02091 5/21/2019 COM/SUPPORT
MachXO3D Soft Error Detection (SED)/Correction (SEC) Usage Guide
FPGA-TN-02124 0.90 5/21/2019 PDF 1.1 MB
MachXO3D Programming and Configuration Usage Guide
FPGA-TN-02069 0.9 5/21/2019 PDF 1.7 MB
MachXO3D sysCLOCK PLL Usage Guide
FPGA-TN-02070 0.90 6/16/2019 PDF 1.8 MB
MachXO3D sysI/O Usage Guide
FPGA-TN-02068 0.90 6/16/2019 PDF 1.1 MB
Using Hardened Control Functions in MachXO3D Devices Reference Guide
FPGA-TN-02119 0.90 8/5/2019 PDF 2.2 MB
Power Decoupling and Bypass Filtering for Programmable Devices
TN1068 1.0 5/1/2004 PDF 31.4 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 4.1 5/20/2019 PDF 4.6 MB
Using Hardened Control Functions in MachXO3D Devices
FPGA-TN-02117 0.91 7/24/2020 PDF 1.7 MB
Implementing High-Speed Interfaces with MachXO3D Usage Guide
FPGA-TN-02065 1.0 7/28/2020 PDF 2.1 MB
Memory Usage Guide for MachXO3D Devices
FPGA-TN-02066 1.0 7/24/2020 PDF 4.6 MB
MachXO3D Hardware Checklist
FPGA-TN-02104 1.0 7/24/2020 PDF 782.2 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
MachXO3D 256-Pin caBGA Package Migration File
1.0 5/21/2019 CSV 15 KB
MachXO3D-9400 Pinout
1.0 5/21/2019 CSV 28.1 KB
MachXO3D 72-Pin QFN Package Migration File
1.0 5/21/2019 CSV 4.7 KB
MachXO3D-4300 Pinout
1.02 6/1/2020 CSV 17.5 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Using MachXO3D ESB to implement ECDSA Generation/Verification - Source Code
1.0 5/21/2019 ZIP 974.6 KB
Using MachXO3D ESB to implement SHA256 - Source Code
1.0 5/21/2019 ZIP 989.3 KB
Using MachXO3D ESB to implement AES128/256 Encryption/Decryption
FPGA-RD-02056 1.0 5/21/2019 PDF 781.8 KB
Using MachXO3D ESB to implement HMAC SHA256 - Documentation
FPGA-RD-02052 1.0 5/21/2019 PDF 858.3 KB
Using MachXO3D ESB to implement HMAC SHA256 - Source Code
1.0 5/21/2019 ZIP 816.3 KB
Using MachXO3D ESB to implement ECIES Encryption/Decryption
FPGA-RD-02055 1.0 5/21/2019 PDF 973.3 KB
Using MachXO3D ESB to implement ECIES Encryption/Decryption - Source Code
1.0 5/21/2019 ZIP 911.8 KB
Using MachXO3D ESB to implement ECC Key Pair Generation
FPGA-RD-02057 1.0 1/10/2020 PDF 946 KB
Using MachXO3D ESB to implement ECDSA Generation/Verification
FPGA-RD-02053 1.0 5/21/2019 PDF 1 MB
Using MachXO3D ESB to implement ECC Key Pair Generation - Source Code
1.0 5/21/2019 ZIP 823.3 KB
Using MachXO3D ESB to implement AES128/256 Encryption/Decryption - Source Code
1.0 5/21/2019 ZIP 712.9 KB
Using MachXO3D ESB to implement SHA256
FPGA-RD-02054 1.0 5/21/2019 PDF 1000.5 KB
SPI to WISHBONE Configuration Interface Bridge - Documentation
FPGA-RD-02191 1.0 5/16/2020 PDF 1.6 MB
I2C to WISHBONE Configuration Interface Bridge - Documentation
FPGA-RD-02190 1.0 5/16/2020 PDF 1.5 MB
I2C to WISHBONE Configuration Interface Bridge - Source Code
FPGA-RD-02190 1.0 5/16/2020 ZIP 1.3 MB
SPI to WISHBONE Configuration Interface Bridge - Source Code
FPGA-RD-02191 1.0 5/16/2020 ZIP 1.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice MachXO3D OrCAD Capture Schematic Library (OLB)
1.0 5/21/2019 ZIP 22.1 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
MachXO3D Product Brief
I0268 2.0 9/16/2020 PDF 576.5 KB
Product Selector Guide
I0211 27.0 9/17/2020 PDF 8.9 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
BG256 XO3D
1.0 5/21/2019 PDF 23.2 KB
BG484 XO3D
1.0 5/21/2019 PDF 23.3 KB
BG400 XO3D
1.0 5/21/2019 PDF 23.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Building Comprehensive Hardware Security
WP0018 1.0 5/21/2019 PDF 250.2 KB
Next-Generation MachXO3D FPGAs Make Automotive Space Secure
WP0027 1.0 9/17/2020 PDF 583.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
[BSDL] LCMXO3D-9400C QFN72
1.0 5/21/2019 BSM 40.5 KB
[BSDL] LCMXO3D-9400C CABGA484
1.0 5/21/2019 BSM 70.8 KB
[BSDL] LCMXO3D-9400C CABGA400
1.0 5/21/2019 BSM 65.8 KB
[BSDL] LCMXO3D-9400C CABGA256
1.0 5/21/2019 BSM 54.5 KB
[BSDL] LCMXO3D-4300C QFN72
1.0 5/21/2019
[BSDL] LCMXO3D-4300C CABGA256
1.0 5/21/2019 BSM 47.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice MachXO3D
1.0 5/21/2019 IBS 38.3 MB

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