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    ID
    Family
    Category
    Related To
  • Will it be possible to provide the RoHS Conversion date for a given Lattice part?
    3553
    All Devices
    Reliability and Materials
    Lead Free/RoHS
  • Why does the LatticeECP3 device not support True LVDS outputs on leftand right sides of the device…
    3555
    LatticeECP3
    Implementation
    IO Assistant
  • How many MSI (Message Signaled Interrupt) interrupts can be implemented using Lattice PCIe…
    3515
    LatticeECP3
    Lattice IP/Reference Design
    PCIe
  • Why is there a difference in the bitstream file size witha small logic modification in LatticeECP3?
    3514
    LatticeECP3
    Device Programming
    Diamond Programmer
  • The License that I have received from License admin(Example : license_352.dat ), doesn't work even…
    3547
    ispMACH 4A5
    Licensing
    Lattice Diamond
  • When using Lattice tools with Lattice Diamond Subscription License, an error is produced when the PC…
    3562
    LatticeECP3
    Licensing
    Lattice Diamond
  • What are the different factors that affect device speed, temperature and voltage selection during…
    1587
    All FPGA
    Implementation
    Timing Analysis
  • How or where can I learn to use ORCAstra in my ECP3 design?
    1588
    LatticeECP3
    Debugging
    ORCAstra
  • There is no option to generate bitstream (.bit) for the MachXO device.
    1580
    MachXO
    Device Programming
    Configuration/Programming
  • Why are there two JTAG interfaces in the Platform Manager?
    1535
    Platform Manager
    Architecture
    JTAG
  • When implementing the Linear Feedback Shift Register (LFSR) Arithmetic Module in IPexpress, How do…
    1534
    All FPGA
    Implementation
    IPexpress
  • What is an .elf file in LatticeMico8 Mico System Builder (MSB)?
    1536
    All FPGA
    Lattice IP/Reference Design
    Mico8 Microcontroller
  • Does Lattice have a demo package integrating the CPRI core with an Ethernet MAC, HDLC framer and…
    1515
    LatticeECP3
    Lattice IP/Reference Design
    CPRI
  • What effect does a PCS local/remote fault signal to the 10 Gb+ Ethernet MAC have on the MAC TX and…
    1514
    All FPGA
    Lattice IP/Reference Design
    10Gb+ Ethernet MAC
  • Why is the SERDES Quad C powered by VCCIb instead of supplying 1.2v, or 1.5v with passive…
    1527
    LatticeECP3
    Lattice Evaluation Board
    ECP3-Video Protocol
  • Where is the reference design for SGMII to (G)MII bridge specified in IPUG60 ?
    1524
    LatticeECP3
    Lattice IP/Reference Design
    SGMII
  • What is the default configuration of the I/O pins in a blank MachXO2 device ?
    1528
    MachXO2
    Architecture
    IO
  • Why does it take 4 minutes to program the XP2 FPGA device with the svf file generated by ispVM…
    1501
    LatticeXP2
    Device Programming
    Configuration/Programming
  • Are all IOs of LatticeECP3 in high-impedance state when VCC, VCCIO and other power supplies do not…
    1558
    LatticeECP3
    Architecture
    IO
  • What is the recommended setting for PLL_LOL_SET?
    1577
    LatticeECP2/M
    Architecture
    SERDES/PCS
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