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    ID
    Family
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  • Lattice ispVM: What could cause the \u201CJTAG-NOP\u201D error message in ispVM System tool?
    606
    All Devices
    Device Programming
    ispVM System
  • Lattice ispVM: Can ispVM control the JTAG TCK duty cycle and/or frequency?
    605
    All Devices
    Device Programming
    ispVM System
  • How to clear default/recent projects (.xcf) in the File menu of ispVM?
    600
    All CPLD
    Device Programming
    ispVM System
  • How can I resolve ispDOWNLOAD cable and board Power setup issues?Error: ispDOWNLOAD cable…
    603
    All CPLD
    Device Programming
    Cables
  • :  Is it possible that Flash USERCODE and SRAM USERCODE can be different during…
    6036
    MACHXO3
    Architecture
    Configuration/Programming
  • Lattice Radiant Programmer: Why after changing "Program Control NV Register 1" in Radiant…
    6035
    CrossLink-NX
    Device Programming
    Configuration/Programming
  • Diamond: How to set up a floating license in RHEL7 using only license management files?
    6030
    Other FPGA
    License Installation
    Lattice Diamond
  • Can a SERDES recover clk(such as rxa_pclk or rxb_pclk or rx#_sclk in LatticeSC) be used to drive…
    986
    LatticeSC/M
    Architecture
    SERDES/PCS
  • What is the SERDES channel to channel transmit skew for the LatticeSC?
    985
    LatticeSC/M
    Architecture
    SERDES/PCS
  • What are the possible delay variations expected with the transmit and receive SERDES?
    989
    LatticeSC/M
    Architecture
    SERDES/PCS
  • What's the typical rise time for the LatticeSC SERDES reference clock(external CML input pin)?
    987
    LatticeSC/M
    Architecture
    SERDES/PCS
  • The Lattice SC/M data sheet (DS1005) refers Fibre Channel users to the XAUI section of the data…
    982
    LatticeSC/M
    Architecture
    SERDES/PCS
  • How do I interface an LVPECL clock source to a Lattice SERDES Reference Clocks (which is a CML…
    988
    All FPGA
    Architecture
    IO
  • All Devices: What is the difference of PFU and Logic Cells?
    6083
    All Devices
    Inquiries
    Datasheet
  • Modelsim: How do I convert macro from AHDL to Modelsim since Crosslink IP simulation script is based…
    6027
    CrossLink
    Video & Imaging
  • Radiant: How to set project top level via TCL?
    6028
    CrossLink-NX
    Other
  • ECP2:About the Metastability of ECP2M and the latest FPGA
    6024
    LatticeECP2/M
    Architecture
    Configuration/Programming
  • All Nexus: Can the dedicated Pin JTAG_ENABLE still make the port active again?
    6022
    Certus-NX
  • GbE PCS:Why does the GbE PCS link state machine status signal regularly pulse low even though the…
    980
    All FPGA
    Architecture
    SERDES/PCS
  • ECP5: Is SSC input supported in ECP5?
    6020
    LatticeECP5
    Architecture
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