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Topic
ID
Family
Category
Related To
ECP3 : How long does it take for the SerDes TX PLL to lock?
81
LatticeECP3
Architecture
SERDES/PCS
What do I do with VCCIBx connection of the SERDES channel in TX only mode?
82
LatticeECP3
Architecture
SERDES/PCS
How to solve the issue of "ispVM System doesn't detect parallel port ISP Download Cable" ?
209
All FPGA
Device Programming
ispVM System
All FPGA: What is the initial logic level of a register after power-up?
204
All FPGA
Architecture
General Logic
What are the pin location requirements when using an input clock to capture input data?
202
All FPGA
Customer Board Design
Layout Review
What are the required locations for the 7:1 LVDS pins on the LatticeXP2, LatticeECP2/M or…
203
All FPGA
Customer Board Design
Layout Review
Diamond: How do user get a reasonable I/O timing report when PLL phase shift is very large?
200
All FPGA
Implementation
Timing Analysis
What is the origin of my device?
249
All CPLD
Inquiries
Datasheet
IO Simulation: How to simulate open drain IO/s?
241
All Devices
Entry
Mixed Language
MachXO: How is the TSALL pin used in the MachXO?
246
MachXO
Architecture
IO
What is the difference between an ispGAL and a GAL device?
245
GAL/ispGAL
Architecture
General Logic
MachXO: Is an external pull up required on the SleepN pin?
247
MachXO
Architecture
IO
All FPGA: How does the output register and read enable (RDEN) signal affect Dual Clock…
235
All Devices
Architecture
Memory EBR/Distributed
ispLEVER: Why are the registers of the design being clocked at a faster rate than intended?
231
All Devices
Implementation
Synplicity
ABEL: How to create a schematic symbol for a bus?
232
All CPLD
Entry
Schematic
ispVM: Which device is the number 1 device in the JTAG chain in ispVM?
234
All Devices
Device Programming
ispDaisy Chain Download
Diamond: Why do users have preference items in the trace report with 0 timing score?
212
All FPGA
Implementation
Trace
Diamond: Why does the design trigger warning messages stating Edge or Primary clock is un-routable,…
217
All FPGA
Implementation
PAR
PCS Simulation: Iteration Limit Error
214
All FPGA
Simulation
MTI
Does Lattice perform product analysis with devices from the field?
215
All Devices
Reliability and Materials
Device Materials
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