• Home >
  • Answer Database

Answer Database

Have a question? We've got the answer.

During the holiday period (Dec 24 – Jan 4), response times from our Global Support Team may be longer than usual.

Narrow Your Results


Search within results

Family
Category
Type of Issue
Related To
  • Topic
    ID
    Family
    Category
    Related To
  • DDR2:  What could be wrong if there is no read data valid signal detected from the Lattice DDR2 IP…
    304
    All FPGA
    Lattice IP/Reference Design
    DDR2 SDRAM Controller
  • Lattice ispVM system: Does the Linux version of ispVM support the USB Download cable?
    307
    All Devices
    Device Programming
    ispVM System
  • Which VREF pad should I use between VREF1 and VREF2 for a DDR2 or DDR3 memory controller?
    305
    All FPGA
    Architecture
    DDR Memory Interface
  • Can I program ispPAC-POWR or ispClock products with the Lattice USB ispDownload cable?
    306
    All Mixed Signal
    Device Programming
    Cables
  • LatticeECP3: What should done when the Delay-locked loop (DLL) is not getting locked?
    3013
    LatticeECP3
    Architecture
    PLL/DLL/Clock Routing
  • Can I use all availabe DQS pad in a Lattice FPGA device for my DDR1/2/3 memory controller…
    300
    All FPGA
    Architecture
    DDR/DDR2/DDR3
  • MachXO2: How can shift register delay be optimized?
    3014
    All FPGA
    Architecture
    Memory EBR/Distributed
  • Why cannot I pack two registers with the same clock/clock enable/reset signals into one slice after…
    3017
    All FPGA
    Architecture
    General Logic
  • MachXO2:  Can subLVDS To Parallel Sensor Bridge solution for a MachXO2 device support 1.8V sensor…
    3050
    MachXO2
    Architecture
    IO
  • LatticeECP5: When the packet size is larger than the value defined in Maximum Packet Size register,…
    3051
    All FPGA
    Lattice IP/Reference Design
    Tri-Speed Ethernet MAC
  • When should I custom one SPI Flash with Lattice Diamond Programmer, if the sector format is mixed…
    3053
    All FPGA
    Device Programming
    Diamond Programmer
  • When programming the LatticeECP3 device using a Lattice programming cable, what is the purpose of…
    3052
    LatticeECP3
    Device Programming
    Configuration/Programming
  • When only two Serializer/Deserializer (SerDes) channels are running with 1.4 Gbps on LatticeECP3,…
    3059
    LatticeECP3
    Architecture
    SERDES/PCS
  • I can see the USB serial Bus in Device Manager of Windows , but when I scan for devices in the ispVM…
    3023
    Other FPGA
    Device Programming
    Cables
  • [LatticeECP3]: How does the word alignment signal work in HDMI (High-Definition Multimedia…
    3021
    LatticeECP3
    Lattice IP/Reference Design
    HDMI/DVI Interface
  • DDR2: How to connect the terminations for address, control and data lines for Double Data Rate…
    3026
    LatticeECP3
    Customer Board Design
    Schematic Review
  • All Devices: What are the various ways to produce RAM/ROM in a design and its power-up state?
    3024
    All FPGA
    Architecture
    Memory EBR/Distributed
  • Why the error shows "F140007 Window Registry is set improperly" when I try to open an existing…
    3044
    All CPLD
    Licensing
    ispLEVER
  • Lattice Diamond Programmer: How can I use a SPI Flash Memory although it's not included in the…
    3035
    All Devices
    Device Programming
    Diamond Programmer
  • [Color Space Converter (CSC) IP Core]: What is the meaning of tags_in and tags_out signals?
    3039
    Other FPGA
    Lattice IP/Reference Design
    Color Space Converter
    • Page 1 of 103
    First Previous
    1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
    		Next Last

    ABOUT LATTICE

    SALES

    SUPPORT

    FOLLOW