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ID: 232
Case Type: faq
Category: Entry
Related To: Schematic
Family: All CPLD

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How to create a schematic symbol for a bus in an ABEL module?

ABEL language does not have a way to directly define a bus for pins. The bus is often defined as such with an internally defined bus. Here is an example:

DECLARATIONS
CK pin; "Clock input

Q8..Q0 pin istype 'reg'; "Counter outputs

count = [Q8..Q0]; "Creating internal bus

EQUATIONS
count.clk = CK; "Use internal bus name for logic implementation

count := count + 1;

Problem:

Although the schematic tool allows the user to generate bus on the symbol from any ABEL module, users often get errors similar to the following:

"Logical Error 13534: Signal 'Q_0_' of Submodule 'count512' can't be used in the interface. Only pin is allowed."

This indicates that lower-level signal names do not match with the top-level names. The top-level schematic signal name Q[0:8] is translated into Q_0, Q_1, etc.. They do not match with the Abel pin names Q0, Q1, etc.

Solution:

User can edit the symbol to link the bus name Q[0:8] to the actual pin names Q0...Q8. Following the steps listed below allows user to remove the error.

  1. Open top-level schematic file that contains the symbol with the bus (count512)
  2. Click Edit=>symbol
  3. Click the symbol (count512) in schematic editor
    - The Symbol Editor is opened and count512 is shown
  4. Click Edit=>Attribute=>Pin Name Location
    - A Dialogue Box "Pin Name" is opened, and "Don't Show" is checked
  5. Click the pin port Q[0:8]
    - The Q[0:8] is disable now
  6. Click Add=>Text, then input "Q[0:8]" and put to the symbol
  7. Click Edit=>Attribute=>Pin Attribute
  8. In Pin Attribute Dialogue, click Q[0:8], and change it with Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8
  9. Save the Symbol Editor and close it
  10. Save schematic
Now rerun the design flow and the error message should be gone.