Applications
Industrial & Auto
Aerospace & Defense
Defense Overview
Guidance Systems
Software Defined Radio
Space
UAVs
Solution Stacks
Lattice Automate
Lattice Drive
Lattice mVision
Lattice sensAI
Lattice Sentry
Automotive
Automotive Overview
ADAS / Driver Assistance
Functional Safety
Infotainment
Quality & Reliability
Factory Automation
Functional Safety
Machine Vision
PLCs
Robotics
Other Industrial
Medical
Video Surveillance
Comms & Computing
Client Computing
Notebooks / PCs
Printers
Tablets
Solution Stacks
Lattice mVision
Lattice ORAN
Lattice sensAI
Lattice Sentry
Datacenter Systems
Platform Firmware Resiliency
Servers
Storage
Switches
Wireless
5G Open RAN
HetNet Small Cells
Low Power Radios
Millimeter Wave Radios
Wireline
10 Gbps Ethernet MAC
Hitless Updates
Intelligent SFP
RGMII to GMII Bridge
Consumer
Prosumer Electronics
IoT & Wearables
VR Head Mounted Display
Smart Home
Consumer Robots & Toys
Home Control & Security
Solution Stacks
Lattice mVision
Lattice sensAI
Products
FPGAs & Other Devices
Control & Security FPGA
MachXO5T-NX
MachXO5-NX
Mach-NX
MachXO3D
MachXO3
MachXO2
L-ASC10
Platforms
Lattice Avant
Lattice Nexus
General Purpose FPGA
Avant-E
CertusPro-NX
Certus-NX
ECP5 & ECP5-5G
LatticeECP3
LatticeXP2
Ultra Low Power FPGA
iCE40 UltraPlus
iCE40 Ultra
iCE40 UltraLite
iCE40 LP/HX
Video Connection FPGA
CrossLinkU-NX
CrossLink-NX
CrossLinkPlus
CrossLink
VIEW ALL DEVICES →
Software Tools
Software Tools
Lattice Diamond
Lattice Propel
Lattice Radiant
Lattice sensAI Studio
Neural Network Supplies
Software Licensing
VIEW ALL SOFTWARE TOOLS →
Solutions
Solutions
Community Sourced
Demos
IP Cores
Kits & Boards
Reference Designs
Programming Hardware
Solution Stacks
Lattice Automate
Lattice Drive
Lattice mVision
Lattice ORAN
Lattice sensAI
Lattice Sentry
VIEW ALL SOLUTIONS →
Support
Technical Support
Support
Answer Database
Get Technical Support
HSPICE I/O Kit Request
General Inquiries
EXPLORE HELP CENTER →
Software Licensing
Software Licensing
Tools Device Support
Purchase Software License
New IP License Request
Quality & Reliability
Quality & Reliability
Quality & Reliability Information
Export Classification Information
Product Change Notifications (PCNs)
Part Number Reference Guide
Services
Design Services
Lattice Design Group
Lattice Partner Network
Product Services
Programming
3rd Party Programming Support
Programming Service Partners
Secure Supply Chain
Lattice SupplyGuard
Training
Lattice Insights
Discontinued Products
Mature & Discontinued Devices
Legacy Devices & Software
Legacy Products
FPGA Software Archive
Silicon Image Software Archive
Buy
Americas Sales
Sales Locator
Brazil
Canada
Mexico
Puerto Rico
USA
VIEW ALL →
Europe & Africa Sales
Sales Locator
Finland
France
Germany
Israel
Italy
Norway
Spain
Sweden
United Kingdom
VIEW ALL →
Asia Pacific Sales
Sales Locator
Australia
China
India
Indonesia
Japan
Singapore
South Korea
Taiwan
Vietnam
VIEW ALL →
Online Store
Lattice Products
Silicon Devices
Software, Cables, & Boards
BUY ONLINE →
Discontinued Products
Discontinued Products
Rochester Electronics
Arrow Electronics
Blog
About Lattice
About Lattice
About Lattice
About the Company
Environmental Social Governance
Contact Us
Investor Relations
Investor Relations
Investor Overview
Online Investor Kit
Investor FAQ
Board Of Directors
Management
Corporate Governance
SEC Filings
Quarterly Earnings
Analysts
Ethics
Newsroom
Newsroom
Announcements
Blogs
Upcoming Product Events
Image Library
Video Library
Webinar Library
Media Contacts
Careers
Careers
Careers Homepage
Search Job Openings
Our Benefits
Sign In
Register
en
Home
>
Support
>
Answer Database
Answer Database
Have a question? We've got the answer.
Narrow Your Results
Search within results
Family
All CPLD (52)
All Devices (383)
All FPGA (408)
All ispClock (8)
All Mixed Signal (14)
All Power Management (44)
ASSP-Wired (Silicon Image) (25)
ASSP-Wireless(Silicon Image) (1)
Avant-E (5)
Certus-NX (54)
CertusPro-NX (126)
CrossLink (158)
CrossLink-NX (27)
Crosslink-NX (59)
GAL/ispGAL (8)
iCE40 (55)
iCE40 Ultra (16)
iCE40 Ultra Lite (6)
iCE40 UltraLite (5)
iCE40 UltraPlus (41)
ispClock 5400D (10)
ispClock 5600A (9)
ispClock 5600V (1)
ispLSI1000 (2)
ispLSI2000 (2)
ispLSI5000 VE (1)
ispMACH 4000 (40)
ispMACH 4A5 (5)
ispPAC (1)
LatticeEC (1)
LatticeECP (1)
LatticeECP2 (7)
LatticeECP2/M (55)
LatticeECP3 (249)
LatticeECP5 (103)
LatticeSC/M (45)
LatticeXP (2)
LatticeXP2 (60)
Mach-NX (8)
MachXO (33)
MachXO2 (187)
MACHXO3 (91)
MACHXO3D (19)
MACHXO5 (17)
Other CPLD (5)
Other FPGA (25)
Other Mixed Signal (3)
Platform Manager (32)
Platform Manager ll (23)
Power Manager (2)
Power Manager II (119)
Category
ADC (2)
Architecture (618)
Boot Modes (1)
Communications (1)
Connectivity (2)
Customer Board Design (99)
Debugging (53)
Device Modeling (28)
Device Programming (356)
Diamond (26)
Digital Signal Processing (2)
Documentation (6)
DSP (1)
EBR/Large RAM (1)
Embedded Programming (5)
Entry (41)
Ethernet (6)
Ethernet Suite (3)
Evaluation Board (2)
External Memory Interfaces (DDR3, DDR4, LPDDR4, etc.) (2)
Fabric (2)
General Inquiry (2)
HPIO (LVDS, SSTL, HSTL, etc.) (2)
iCEcube2 (3)
Implementation (259)
Inquiries (79)
Installation (56)
IntelliProp (1)
ISPLever/ISPLeverClassic (1)
Lattice Evaluation Board (50)
Lattice IP/Reference Design (216)
Lattice MACO Cores (5)
License Error (1)
License Installation (4)
Licensing (45)
Memory Controllers (1)
MICO8/MICO32 (3)
MIPI D-PHY RX/TX (3)
Modification (1)
New License Request (2)
Notification (2)
OEM Simulation Tool (ModelSim) (5)
Oregano Systems (1)
Other (44)
PAC-Designer (55)
PCI Express Suite (16)
PCIe (11)
PLD Applications (1)
PLL/Clocks/Clock Tree (4)
Processor, Controller & Peripheral (9)
Programming and Configuration (17)
Propel (RISC-V) (16)
Radiant (38)
RD-Processor, Controller & Peripheral (1)
Reliability and Materials (38)
Security (6)
Sentry (1)
Serdes/PCS (4)
Simulation (79)
UART (2)
Update Existing License (1)
Video & Imaging (18)
Video and Display (6)
Video and Display Suite (1)
WRIO (LVCMOS, LVTTL, SubLVDS, etc.) (2)
Type of Issue
AI/Machine Learning (2)
Architecture (20)
Audio, Video, and Image Processing (3)
Connectivity (21)
Documentation (133)
Hardware (1059)
IP Core (70)
IP/Reference Design (225)
Other (23)
Processor, Controllers, Peripherals (2)
Programming and Configuration (32)
Reference Design (13)
Sales (1)
Schematics/Layout Review (1)
Software (991)
Software Licensing (14)
Solution Stack (1)
Timing Closure/Analysis (15)
Wired/Wireless (4)
Related To
10Gb+ Ethernet MAC (1)
2.5Gb Ethernet MAC (1)
2D Scaler (3)
3rd Party (6)
5V/3.3V Hot Swap Controller (1)
7:1 LVDS Video (3)
ABEL (4)
Adapters (2)
Aldec (50)
All (4)
Appnote/Technote (23)
ASIC Block (MACO) (4)
Attributes/Directives (6)
Bitstream/JEDEC Generation (7)
Block Modular Design (1)
Block Viterbi Decoder (1)
Board Debug (17)
BSDL (5)
Cables (28)
Closed-loop Trim/Fault Logger (5)
Color Space Converter (1)
Compile/Fit (11)
Configuration (1)
Configuration/Programming (166)
Constraint-Pref Editor (14)
CPRI (4)
Customer Board (9)
Data Retention (1)
Datasheet (29)
DDR Memory Interface (12)
DDR SDRAM Controller (1)
DDR/DDR2/DDR3 (8)
DDR2 SDRAM Controller (4)
DDR3 SDRAM Controller (27)
DELPHI (1)
Deployment Tool (11)
Design Planner (9)
Design Utilities (7)
Device Materials (17)
Diamond Programmer (36)
DSP (2)
ECP/EC-Mico32 DSP (1)
ECP/EC-Standard (1)
ECP3-I/O Protocol (2)
ECP3-Serial Protocol (1)
ECP3-Versa (1)
ECP3-Video Protocol (1)
ECP5 Versa (1)
Embedded Functional Block (EFB) (12)
Embedded Programming (24)
Engineering Kits (1)
EPIC (3)
Ethernet 1/10 Gigabit FlexiMAC (5)
Examples (2)
FFT Compiler (2)
FIR Filter Generator (1)
Fitter (5)
General Logic (21)
Generic DDR (12)
HDL Explorer (3)
HDMI/DVI Interface (7)
HDR-60 Eval Board (9)
Help Files (4)
Hercules-Standard (3)
HVOUT (1)
I2C (18)
I2C Slave Peripheral (2)
IBIS (18)
iCECube2 (1)
IEEE 1588 Clock_M (1)
Inquiries (2)
Interleaver/De-interleaver (1)
IO (141)
IO Assistant (4)
IP (2)
IP Core License (1)
IP/Reference Design Inquiries (17)
IPexpress (16)
ispClock (1)
ispClock 5312S (2)
ispClock 5620A (1)
ispDaisy Chain Download (1)
ispLEVER (10)
ispMACH 4000ZE Pico Dev Kit (3)
ispVM Embedded (19)
ispVM System - Win ALL (1)
ispVM System (65)
ispVM System-Linux (1)
ispVM System-Win 7 (1)
ispVM System-Win Vista (1)
ispVM System-Win XP (1)
JTAG (10)
Lattice Diamond (29)
Lattice Evaluation Boards (3)
Lattice Evaluation Boards (All) (6)
Lattice Radiant (3)
Lattice Simulator (2)
LatticeMico32 (15)
Layout (12)
Layout Review (5)
Lead Free/RoHS (1)
Lifetime (2)
Linux (7)
LogiBuilder (20)
LSE (Lattice Synthesis Engine) (2)
MachXO Control Dev Kit (1)
MachXO2 1200 Breakout (1)
MAP (12)
Memory EBR/Distributed (12)
Mico32(MSB) (13)
Mico8 Microcontroller (13)
MIPI CSI2 RX (3)
MIPI CSI2 TX (1)
MIPI D-phy (3)
MIPI DSI RX (2)
MIPI DSI TX (1)
Mixed Language (3)
Model 300 Programer (1)
Module/IP Manager (2)
MTI (11)
NC-Verilog (2)
NGD (1)
ORCAstra (7)
Oscillator (6)
Other (71)
PAC-Designer (2)
Packaging (18)
PAR (32)
PCI Express x4 Endpoint (1)
PCIe (33)
PCN (2)
PCS Pipe (2)
Platform Manager Development Kit (6)
PLL/DLL/Clock Routing (85)
Power (40)
Power Calculator (6)
Power Sequence (22)
Preference Views (2)
Processor PM Dev Kit (1)
Project Navigator (9)
Radiant Programmer (1)
RAM-Type Interface for Embedded User Flash Memory (1)
Ref. Design (1)
Reliability (17)
Reveal (38)
RGMII to GMII Bridge (1)
Schematic (52)
Schematic Review (18)
Security (2)
SERDES/PCS (102)
Serial RapidIO (1)
SGMII (2)
SGMII and Gb Ethernet PCS (7)
SGMII and Gigabit Ethernet PCS P P 1 (1)
Simulation (5)
Simulation Files (2)
Soft Error Detection (SED) (2)
SPI (3)
SPI WISHBONE Controller (1)
SPI4.2 (4)
Spice (1)
SSO (1)
SSO Analysis (3)
Synopsys (2)
Synopsys (VCS) (2)
Synplicity (13)
Synplify Pro (1)
Synthesis (29)
Third Party Tools (4)
Timing Analysis (33)
Timing Closure (10)
Trace (9)
TRIM (2)
TRIM Usage (8)
Triple Speed 10/100/1G Ethernet MAC (1)
Tri-Rate SDI PHY (3)
Tri-Speed Ethernet MAC (6)
Tutorials (2)
UART (1)
User Flash Memory (UFM) (4)
User Guides (9)
Verilog (4)
VHDL (7)
VMON Usage (1)
VMONs (1)
Web Site (1)
Win 7 (5)
Win Other (1)
Win Vista (5)
Win-All (10)
XAUI 10Gb Ethernet AUI (3)
XP2 Brevia Dev Kit (1)
XpressLite PCIe x1 Controller (1)
Topic
ID
Family
Category
Related To
What are the pin location requirements when using an input clock to capture input data?
202
All FPGA
Customer Board Design
Layout Review
Can ORCAstra access and manipulate data in a file from a Script Window or Visual Window?
205
All FPGA
Debugging
ORCAstra
What is the initial logic level of a register after power-up?
204
All FPGA
Architecture
General Logic
How to solve the issue of "ispVM System doesn't detect parallel port ISP Download Cable" ?
209
All FPGA
Device Programming
ispVM System
I am having installation problems with ispLEVER Starter.
208
All Devices
Installation
Win-All
What are the required locations for the 7:1 LVDS pins on the LatticeXP2, LatticeECP2/M or…
203
All FPGA
Customer Board Design
Layout Review
How do I get a reasonable I/O timing report when PLL phase shift is very large?
200
All FPGA
Implementation
Timing Analysis
What is the origin of my device?
249
All CPLD
Inquiries
Datasheet
How can I simulate open drain IO/s?
241
All Devices
Entry
Mixed Language
How is the TSALL pin used in the MachXO?
246
MachXO
Architecture
IO
Is there ESD (Electro Staic Discharge) protection circuitry on the MachXO?
248
MachXO
Architecture
IO
What is the difference between an ispGAL and a GAL device?
245
GAL/ispGAL
Architecture
General Logic
What is the detailed power up sequence for a MachXO device?
242
MachXO
Architecture
Power Sequence
Is an external pull up required on the MachXO SleepN pin?
247
MachXO
Architecture
IO
How does the output register and read enable (RDEN) signal affect Dual Clock FIFO (FIFO_DC)?
235
All Devices
Architecture
Memory EBR/Distributed
Why are the registers being clocked at a faster rate than intended?
231
All Devices
Implementation
Synplicity
How to create a schematic symbol for a bus in an ABEL module?
232
All CPLD
Entry
Schematic
Which device is the number 1 device in the JTAG chain?
234
All Devices
Device Programming
ispDaisy Chain Download
Why am I getting an error in "map" when I want to reset my IP cores with different resets? The error…
218
All FPGA
Architecture
General Logic
Why do I have items in my trace report with 0 timing score?
212
All FPGA
Implementation
Trace
Page 1 of 133
First
Previous
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Next
Last