Answer Database

Have a question? We've got the answer.

Narrow Your Results


Search within results

Family
Category
Type of Issue
Related To
  • Topic
    ID
    Family
    Category
    Related To
  • Can a ECP2 dual boot application be set up to load the golden bitstream rather than the primary?
    897
    LatticeECP2
    Device Programming
    Configuration/Programming
  • ispVM: What does the "AS" or "ES" suffixes mean on the  ispVM device part number selections?
    892
    All Devices
    Device Programming
    ispVM System
  • ispVM: Can ispVM be run on the Windows Vista 64-bit or Windows XP 64-bit O/S?
    894
    All Devices
    Device Programming
    ispVM System
  • LatticeXP2: How to access LatticeXP2 User Electronic Signature (UES)?
    896
    LatticeXP2
    Inquiries
    Appnote/Technote
  • Do user needs to connect all wires from Lattice Programming Cable to an evaluation board?
    891
    All Devices
    Device Programming
    Cables
  • Lattice Radiant: Why can't I program the external SPI Flash when TransFR is enabled?
    6980
    CertusPro-NX
    Radiant
  • MachXO3/MachXO2:How to monitor INITN in case the current package do not pin-out initn?
    6983
    MachXO2
    Programming and Configuration
  • MachXO5-NX Development Board: How to access the MachXO5-NX Development Board via SSPI using onboard…
    6984
    MACHXO5
    Evaluation Board
  • Radiant 2022.1 SP1 and SDR IP: How to solve the PAR (R2022.1.1) error or Map (R2023.1) error?
    6969
    CertusPro-NX
    Radiant
  • How to solve the correlation issue when using LVDS receiver input (i.e. lvs180axxxeaaaaabain)?
    6962
    CertusPro-NX
    HPIO (LVDS, SSTL, HSTL, etc.)
  • PCIe for Nexus FPGAs: Does PCIe IP supports full PCIe X1 component/block and configuration via LMMI…
    6961
    Certus-NX
    PCIe
  • Serdes/PCS: How to know if the two SerDes data rates can be generated with the same reference clock…
    6965
    CertusPro-NX
    Serdes/PCS
  • CertusPro-Nx: What are the recommended LPDDR4 trace impedance for CertusPro-NX devices?
    6963
    CertusPro-NX
    External Memory Interfaces (DDR3, DDR4, LPDDR4, etc.)
  • Lattice Radiant: What are the meanings of the values of Pin Pair Delay in Radiant?
    6950
    All FPGA
    Radiant
  • All Nexus Families: How are the commands and bitstream sent in the Nexus device via Quad (x4) Slave…
    6954
    Certus-NX
    Programming and Configuration
  • MachXO3D: How are status and errors reported in TRNG( True Random Numbers Generator ) Feature?
    6959
    MACHXO3D
    Security
  • MachXO3D: Does the raw TRNG output always go through SHA-256 as a conditioner?
    6958
    MACHXO3D
    Security
  • MachXO3D: Does MachXO3D claim to be IID (Independent and Identically Distributed)?
    6956
    MACHXO3D
    Security
  • MachXO3D: What is the architecture of TRNG( True Random Number Generator ) Feature?
    6957
    MACHXO3D
    Security
  • CertusPro-NX: Is it possible to implement JTAG Soft lock/unlock in CertusPro-NX?
    6953
    CertusPro-NX
    Security
    • Page 1 of 103
    First Previous
    1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
    		Next Last

    ABOUT LATTICE

    SALES

    SUPPORT

    FOLLOW