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    ID
    Family
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  • The LatticeXP2 device does not have a sub-LVDS input type, can I still receive sub-LVDS output…
    881
    LatticeXP2
  • The XP2 device does not have a mini-LVDS output type, can I still drive mini-LVDS inputs with the…
    879
    LatticeXP2
  • Should I add external series resistors to my parallel bus to improve the signal integrity?
    852
    All Devices
  • Why can't I drive a long PCB trace with a low current setting and get good signal quality?
    850
    All Devices
  • Should I add a series inductor between my voltage regulator output and VCC core?
    848
    All Devices
  • My device has a 3.3v VCCIO, can the device IO drive an LED directly?
    840
    All Devices
  • What is the difference between a .bit file and a .jed file?
    617
    All Devices
    Other
  • Why does the following error occur: "ERROR - Environment variable 'TEMP' is set to a non-writable…
    492
    All FPGA
    Other
  • I configure a Lattice ECP2/M device with an Atmel SPI Flash. Supposedly the CCLK should run 120…
    424
    LatticeECP2/M
    Architecture
  • How can the default/recent projects (.xcf) be cleared in the File menu of ispVM?
    1318
    All Devices
  • Why is a DRC error generated associated with the PCI Core signal/pin serrn (SERR#)?
    1315
    All Devices
  • How many DDR memory interfaces can be implemented on a single part?
    1076
    All FPGA
  • In PCI Express x4 core v3.3, when do we need to set VCO auto-band options in the auto-configure text…
    1062
    LatticeECP2/M
  • I have a 3-stage shift register, the software always implement it in a dual-port RAM, how can I…
    1060
    All FPGA
  • Why do I receive notices that my evaluation version of Aldec is about to expire. I upgraded to…
    1053
    All Devices
  • How do I get rid of the License error thrown out by the Aldec Simulator?
    3568
    ispMACH 4000
  • Is there an easy way to modify some Embedded Block RAM (EBR) data before running bitgen with…
    3538
    LatticeECP3
    Implementation
    EPIC
  • Where can I find more information related to Lattice Intellectual Property (IP)? Like -IP Suites,…
    3517
    All FPGA
    Lattice IP/Reference Design
    PCIe
  • Are the MIPI CSI2 and DSI reference designs supported on iCE40?
    3505
    iCE40
    Lattice IP/Reference Design
  • From where do I download the Mature Software from Lattice?
    3473
    Other FPGA
    Other
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