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  • Topic
    ID
    Family
    Category
    Related To
  • How long does it take for the SerDes TX PLL to lock?
    81
    LatticeECP3
    Architecture
    SERDES/PCS
  • What do I do with VCCIBx connection of the SERDES channel in TX only mode?
    82
    LatticeECP3
    Architecture
    SERDES/PCS
  • What are the pin location requirements when using an input clock to capture input data?
    202
    All FPGA
    Customer Board Design
    Layout Review
  • Can ORCAstra access and manipulate data in a file from a Script Window or Visual Window?
    205
    All FPGA
    Debugging
    ORCAstra
  • How to solve the issue of "ispVM System  doesn't detect  parallel port ISP Download Cable" ?
    209
    All FPGA
    Device Programming
    ispVM System
  • What is the initial logic level of a register after power-up?
    204
    All FPGA
    Architecture
    General Logic
  • I am having installation problems with ispLEVER Starter.
    208
    All Devices
    Installation
    Win-All
  • What are the required locations for the 7:1 LVDS pins on the LatticeXP2, LatticeECP2/M or…
    203
    All FPGA
    Customer Board Design
    Layout Review
  • How do I get a reasonable I/O timing report when PLL phase shift is very large?
    200
    All FPGA
    Implementation
    Timing Analysis
  • What is the origin of my device?
    249
    All CPLD
    Inquiries
    Datasheet
  • How can I simulate open drain IO/s?
    241
    All Devices
    Entry
    Mixed Language
  • How is the TSALL pin used in the MachXO?
    246
    MachXO
    Architecture
    IO
  • What is the difference between an ispGAL and a GAL device?
    245
    GAL/ispGAL
    Architecture
    General Logic
  • Is there ESD (Electro Staic Discharge) protection circuitry on the MachXO?
    248
    MachXO
    Architecture
    IO
  • What is the detailed power up sequence for a MachXO device?
    242
    MachXO
    Architecture
    Power Sequence
  • Is an external pull up required on the MachXO SleepN pin?
    247
    MachXO
    Architecture
    IO
  • How does the output register and read enable (RDEN) signal affect Dual Clock FIFO (FIFO_DC)?
    235
    All Devices
    Architecture
    Memory EBR/Distributed
  • Why are the registers being clocked at a faster rate than intended?
    231
    All Devices
    Implementation
    Synplicity
  • How to create a schematic symbol for a bus in an ABEL module?
    232
    All CPLD
    Entry
    Schematic
  • Which device is the number 1 device in the JTAG chain?
    234
    All Devices
    Device Programming
    ispDaisy Chain Download
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