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    ID
    Family
    Category
    Related To
  • All FPGA: What is the recommended Bypass Capacitor size for DDR3 Power filter? Can I use a small…
    6532
    All FPGA
    Customer Board Design
    Schematic
  • Certus-NX: What are the recommendation on power filtering for DDR3? (BYPASS CAPACITORS TO GROUND,…
    6531
    Certus-NX
    Customer Board Design
    Schematic
  • All FPGA: Why are the power rails for DDR3_VTT and VCC_1V5 connected to one another?
    6530
    All FPGA
    Customer Board Design
    Schematic
  • Reveal Inerter synthesis error:  with mode 'out' cannot be read.
    6538
    CertusPro-NX
    Debugging
    Reveal
  • Radiant and Diamond: Are there any legal concerns when publishing bitstream files and project files…
    6533
    ispMACH 4000
    Radiant
    Other
  • CertusPro-NX: NC(No Connections) pins of CertusPro NX should be connected to GND, or can be left…
    6509
    CertusPro-NX
    Fabric
  • LatticeMicoSystem: Error: "Tcl8.5 is not installed! Please re-install again!
    6500
    Other FPGA
    Debugging
  • Deployment Tool: Can I read or verify the USERMODE via sea/iea and sed/ied files?
    6505
    MACHXO3
    Programming and Configuration
    Diamond Programmer
  • MachXO2: Should I power up Vcc or Vccio first in my board design? 
    6503
    MachXO2
    Customer Board Design
    Schematic Review
  • Certus-NX: What is the Maximum Current per bank?
    6502
    Certus-NX
    WRIO (LVCMOS, LVTTL, SubLVDS, etc.)
  • All devices:  Does Lattice devices have a power-down sequence?
    6501
    All Devices
    Architecture
    Power
  • Lattice Diamond: What is the behavior of my generated bitstream if i do not have any…
    6508
    MACHXO3D
  • Lattice Diamond: Why are there no paths analyzed for MAXDELAY constraint. How to use MAXDELAY…
    6507
    MachXO2
  • Lattice Diamond: What is the meaning between black and green IC Icon in the Post Map Resources?
    6577
    All CPLD
  • MachXO2/MachXO3: Why is the IO state locked during TransFR Operation of MACHXO3 device?
    6574
    MACHXO3
    Device Programming
    Configuration/Programming
  • Lattice Nexus devices using Reveal: no output from LVDS IP
    6575
    CrossLink-NX
    Debugging
    Reveal
  • Diamond: Why does Reveal Inserter with CrossLink device only allows one trigger expression?
    6545
    CrossLink
    Debugging
  • Why does the change in the Feature Row appear to take effect immediately when using a background…
    6548
    MachXO2
    Device Programming
    Embedded Programming
  • CrossLink-NX: What is the accuracy of ADC Internal Reference Voltage?
    6510
    CrossLink-NX
    ADC
    Other
  • MIPI CSI-2 / DSI D-PHY Receiver: What is the use of the RX_FIFO in the MIPI D-phy RX IP?
    6519
    CrossLink-NX
    Video & Imaging
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