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    ID
    Family
    Category
    Related To
  • Mico System Builder: error occurs while debugging the C code: "Malformed response to offset query,…
    4419
    LatticeECP3
    Debugging
    Reveal
  • All Devices: Where to find the I2C Embedded Source Code?
    6311
    CrossLink-NX
    Device Programming
  • LatticeECP2/M\u200B: How can customers generate a BSDL model for their JEDEC file?
    6310
    LatticeECP2/M
  • Lattice Radiant: What is drive strength of an output when set to 50RS and how it is applied?
    6315
    Certus-NX
  • CertusPro-NX: Does High Performance IO supports hot socketing?
    6398
    CertusPro-NX
  • All Nexus: What is the default state of Nexus Platform's sysCONFIG pins?
    6395
    CertusPro-NX
    Device Programming
    Configuration/Programming
  • How to resolve the JTAG read/write access issue with Lattice's FPGA that uses JTAG voltage other…
    6394
    CertusPro-NX
    Device Programming
    Configuration/Programming
  • [Radiant] Tri-speed Ethernet MAC: How to resolve Tri-speed Ethernet MAC version 1.4.0 synthesis…
    6968
    All FPGA
    Ethernet
  • Radiant 2022.1 SP1 and SDR IP: How to solve the PAR (R2022.1.1) error or Map (R2023.1) error?
    6969
    CertusPro-NX
    Radiant
  • How to solve the correlation issue when using LVDS receiver input (i.e. lvs180axxxeaaaaabain)?
    6962
    CertusPro-NX
    HPIO (LVDS, SSTL, HSTL, etc.)
  • PCIe for Nexus FPGAs: Does PCIe IP supports full PCIe X1 component/block and configuration via LMMI…
    6961
    Certus-NX
    PCIe
  • Serdes/PCS: How to know if the two SerDes data rates can be generated with the same reference clock…
    6965
    CertusPro-NX
    Serdes/PCS
  • CertusPro-Nx: What are the recommended LPDDR4 trace impedance for CertusPro-NX devices?
    6963
    CertusPro-NX
    External Memory Interfaces (DDR3, DDR4, LPDDR4, etc.)
  • PCIe for Nexus FPGAs: Does the vc_tx_valid_i can be delayed (insert 3 clock cycles) during long…
    6979
    Certus-NX
    PCIe
  • PCIe for ECP5: How to disable the Advanced Error Reporting (AER) of the ECP5 PCIe IP ?
    6978
    LatticeECP5
    PCIe
  • [CertusPro-NX] Serdes/PCS: Why does the MPCS-8b10b IP fails in x8 lane simulation?
    6977
    CertusPro-NX
    Serdes/PCS
  • PCIe: How to view the PCIe configuration space on a specific domain in Linux machine?
    6976
    All FPGA
    PCIe
  • MachXO3D: The VCCIO0 ( Bank 0 ) is tied to 1.8V making the JTAG interface 1.8 V. Can I pull the TDO…
    6975
    MACHXO3D
    Programming and Configuration
  • MachXO2/MachXO3: Is it possible to turn save power by turning off internal oscillator of MachXO2 and…
    6970
    MachXO2
    Programming and Configuration
  • What is the spec of 'sync_clk_i' of MIPI D-PHY Rx IP? Does the signal require to be in synced with…
    6946
    CrossLink-NX
    MIPI D-PHY RX/TX
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