Occasionally in congested designs a conflict occurs resulting in an unroutable condition during the Place and Route (PAR) phase of a design. The conflict can be due to components that have been placed by user constraints, or by the decisions made by the placement tool. It may become necessary for a designer to specify the locations of the PLL's, DLL's, and CLKDIV's to achieve optimal performance for the Edge clock and Primary clock resources.
PAR may give an error or a warning message that either a Primary or Edge clock cannot be accessed directly. The result is that PAR uses a general route to put the clock onto the Primary or Edge clock. To gain insight into Primary / Edge clock usage read the technical note for the device family you are using. For example, the LatticeSC FPGA clock resources are described in TN1098. TN1098 Figure 33 shows the resources available for Edge clocks. TN1098 Table 10 shows the resources available for Primary clocks.
Example: An Edge clock conflict for an LatticeSC design. The design has a PLL using the CLKOP and a receive clock driving a CLKDIV. The design constraints or the placer can place the PLL at PLL_ULCB, and the receive clock is placed such that it drives CLKDIV7D. In this case, PAR will warn the user (so long as the other edge clocks are not used) that one of these clocks is diverted to general routing in order to get around this conflict. The reason for this conflict can be seen in TN1098 Figure 33. Figure 33 shows the primary output of PLL_ULCB can be driven by PCLKT7_0, PCLKT7_3, CLKDIV7D, and PLL_LLCB's CLKOP. The primary clock path is oversubscribed in this instance and PAR may generate a warning:
WARNING - par: edge clock /rdclk driver is PIO/IOL but not placed on sweet site or edge clock branch is occupied, will be routed using generic routing to the branch and may suffer from excessive delay or skew.
In most cases, you can simply change the PLL output (CLKOS to CLKOP, or vise versa) or the PLL location in order to work around an existing pinout. In more congested designs, it may be necessary for you to drive a PLL output to a DLL in order to change the edge clock route in the design. The possible configurations of PLLs to DLLs are given in the PLL/DLL cascading section of TN1098. An example of PLL, DLL, and CLKDIV placement:
LOCATE COMP "" SITE "PLL_LLCB" ;
LOCATE COMP "" SITE "DLL_LRCC" ;
LOCATE COMP "" SITE "CLKDIV7A" ;
In the case of a Primary clock, you should specify which clocks are to use primary routing. The tools will, in most instances, automatically promote these (or other) clocks as required. In a congested design it may become necessary for you to section the clocks into quadrants. You must be careful as the tools will error out if a required clock is not allowed to be routed into the quadrant where its logic is located. An example of locating clocks to specific quadrants:
USE PRIMARY NET "clock1" QUADRANT_BL QUADRANT_BR ;
USE PRIMARY NET "clock2" QUADRANT_TL QUADRANT_TR ;