​​Modern Avionics platforms with Assurance and Security

Enabling Airborne platform with Functional Safety certified and DO-254 solutions

The Avionics industry is a realm of exceptional standards and unyielding reliability. Modern Avionics systems with electronic controls and heightened security requirements must provide advanced functionality while maintaining safety, reliability and assured performance. Leveraging the strength of our ecosystem, Lattice offers a comprehensive DO-254 solution with Intellectual property and tool flow to reduce the risk and accelerate time to market of avionics platforms. Lattice supports functional safety for industrial IEC 61508 and automotive ISO 26262, with TÜV certified design flows that enable applications to be certified. The certified tool chain spans Lattice Diamond and Radiant (including Synplify and ModelSim), with workflows aligned to DO 254 and options such as TMR.

  • Low power FPGAs to meet extended temperature and other harsh environmental constraints 
  • Industry leading fast, secure boot with state of the art security and robust encryption to meet domain specific safety, security and reliability requirements 
  • Sophisticated tool flow with redundancy and isolation design flow in support of Design Assurance Levels

Key Lattice FPGA Features & Benefits

  • From non-volatile FPGAs to mid-range FPGA that scales up to 637 Logic Cells and 28 multi-protocol transceivers optimized for edge connectivity/sensing connectivity, signal conditioning/pre-processing, and safe/deterministic control.
  • Industry leading advanced security features including AES256-GCM, ECDSA 256-521 & RSA 2048-4096 with post quantum resilience, anti-tamper and hardened PUF to secure bitstream and user data and support upgradability to tackle future needs and evolving threats. 
  • Design tools offer latest advancements in scripting, design partitioning, timing analysis, high speed interface debug and third party tools integration for synthesis including TMR, simulation and verification.

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Videos

Video Thumbnail

LDC24 Demo - Logic Fruit Technologies Inc. ARINC 818-3 IP

Leaded Package Overview

Lattice offers leaded packaging services to eliminate the risk for tin-whisker and to improve reliability in presence of high shock and vibration applications.

Lattice Packages Wirebond Flip Chip
Wafer Pad or Bump Lead free Lead free
Substrate bump or pad finish Lead free Lead free
Caps No Caps No Caps
Substrate Solder Balls Leaded Leaded
Package Reflow Leaded Leaded

Known Good Die Product Overview

Lattice offers a wide variety of known good die products, tested to full data sheet specification within the specified temperature range with full traceability for each die shipped.

Family Logic Density Test Method Programmability Temperature Range
LatticeECP3 150K Known Good Die Volatile -40 C to 125 C
LatticeXP2 40K Good Die Non-volatile -40 C to 125 C
ECP5 85K Known Good Die Volatile -40 C to 125 C
MachXO3 10K Known Good Die Non-volatile -40 C to 105 C
Avant 637K Known Good Die Volatile -40C to +125C
Certus-NX 39K Known Good Die Volatile -40C to +125C
CertusPro-NX 96K Known Good Die Volatile -40C to +125C
CrossLink-NX 39K Known Good Die Volatile -40C to +125C

Reference Designs

目标分类参考设计

Reference Design

目标分类参考设计

该参考设计展示了在网络边缘设备应用中实现基于机器学习的目标分类示例。
目标分类参考设计
Close Loop BLDC Motion Control Reference Design

Reference Design

Close Loop BLDC Motion Control Reference Design

Implementation of Industrial high-end encoder on real-time position feedback for speed control in the Closed-loop BLDC motor control system
Close Loop BLDC Motion Control Reference Design
CrossLinkU-NX UVC Streaming Reference Design

Reference Design

CrossLinkU-NX UVC Streaming Reference Design

UVC streaming Reference Design provides a template for video streaming from camera sensor over the USB hard IP in the CrossLinkU-NX device to a USB host.
CrossLinkU-NX UVC Streaming Reference Design
Lattice QSPI to NXP MPU Interface Reference Design

Reference Design

Lattice QSPI to NXP MPU Interface Reference Design

This Lattice and NXP joint solution is designed to implement FlexSPI communication and expedite deployment using the Lattice ECP5 Evaluation Board.
Lattice QSPI to NXP MPU Interface Reference Design
DisplayPort & 视频缩放器参考设计

Reference Design

DisplayPort & 视频缩放器参考设计

Lattice Drive DisplayPort和视频缩放器参考设计可轻松评估各种DisplayPort接口。
DisplayPort & 视频缩放器参考设计

IP Cores

10G Ethernet IP Core

IP Core

10G Ethernet IP Core

The Lattice 10G Ethernet IP Core supports the ability to transmit and receive data between a host processor and an Ethernet network.
10G Ethernet IP Core
25Gb以太网MAC+PHY IP核

IP Core

25Gb以太网MAC+PHY IP核

莱迪思半导体的25G以太网(GbE)IP核支持在主机处理器和以太网网络之间发送和接收数据。
25Gb以太网MAC+PHY IP核
Image Signal Processing IP Cores Suite

IP Core

Image Signal Processing IP Cores Suite

The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
Image Signal Processing IP Cores Suite
MACsec AES256-GCM, High-speed (XIP1213H)

IP Core

MACsec AES256-GCM, High-speed (XIP1213H)

The high-speed MACsec IP core implements the MACsec protocol as standardized in IEEE 802.1AE-2018, defining a security infrastructure for OSI model Layer 2 traffic.
MACsec AES256-GCM, High-speed (XIP1213H)
ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

IP Core

ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

ML-KEM-512/768/1024 is an IP core for post-quantum Key Encapsulation Mechanism (KEM), optimized for a good balance between speed and resource requirements.
ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

Development Kits & Boards

CrossLink-NX评估板

Board

CrossLink-NX评估板

CrossLink-NX评估板载有一片40K逻辑单元的CrossLink-NX FPGA;可轻松访问FPGA上的大多数I/O和PCIe 5G SERDES; 拥有FPGA中间层板卡(FMC)、Raspberry Pi、MIPI CSI-2、D-PHY和通用接头,大大扩展了易用性。
CrossLink-NX评估板
ECP5评估板

Board

ECP5评估板

售价仅为99美元的ECP5评估板拥有一片85K LUT的ECP5-5G FPGA;可轻松访问大多数I/O以及SERDES;更支持Arduino和Raspberry Pi以及通用接口以提高可用性。
ECP5评估板
USB3-GbE VIP IO开发板

Board

USB3-GbE VIP IO开发板

适用于视频接口平台(VIP)的USB 3.0 和千兆以太网输出板
USB3-GbE VIP IO开发板
iCE40 UltraPlus 分线板

Board

iCE40 UltraPlus 分线板

适用于iCE40 UltraPlus 5K版器件的分线板
iCE40 UltraPlus 分线板

Demos

莱迪思ORAN IEEE 1588 PTP安全同步演示

演示

莱迪思ORAN IEEE 1588 PTP安全同步演示

莱迪思ORAN安全同步演示展示了莱迪思带软IP的FPGA如何利用电信1588 PTP和ITU配置文件实现紧密和安全的同步。
莱迪思ORAN IEEE 1588 PTP安全同步演示

Quality Programs

Lattice is committed to Industry Leadership in the supply of high quality programmable logic components and software design tools.

Documentation

快速参考
资讯资源
标题 编号 版本 日期 格式 文件大小
选择全部
Implementing JOTP-051-Compliant Safety Features in Lattice FPGAs
FPGA-TN-02150 1.1 3/15/2021 PDF 855.2 KB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 2.3 10/13/2025 PDF 806.2 KB
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-02174 1.8 10/13/2025 PDF 453.7 KB
标题 编号 版本 日期 格式 文件大小
选择全部
Implementing JOTP-051-Compliant Safety Features in Lattice FPGAs
FPGA-TN-02150 1.1 3/15/2021 PDF 855.2 KB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 2.3 10/13/2025 PDF 806.2 KB
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-02174 1.8 10/13/2025 PDF 453.7 KB
标题 编号 版本 日期 格式 文件大小
选择全部
Defense Solutions Brief
I0271 Rev 1 8/4/2020 PDF 1.6 MB
标题 编号 版本 日期 格式 文件大小
选择全部
A Guide to the Benefits of the Lattice Nexus FPGA Platform for Mission-Critical Applications
WP0028 1.0 1/22/2021 PDF 449.4 KB

Support

技术支持

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