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  • 5G Ethernet IP Core

    IP Core

    5G Ethernet IP Core

    The 5GbE IP core enables high-speed data transfer between a host processor and an Ethernet network, connecting MAC and PHY via XGMII per IEEE 802.3.
    Avant-G, Avant-X 
    Ethernet, PCS, Lattice Avant 
    5G Ethernet IP Core
  • 10G Ethernet IP Core

    IP Core

    10G Ethernet IP Core

    The Lattice 10G Ethernet IP Core supports the ability to transmit and receive data between a host processor and an Ethernet network.
    Avant-G, Avant-X, CertusPro-NX 
    Ethernet, PCS, XGMII, AXI4, Ethernet Bundle, SDR, Avionics 
    10G Ethernet IP Core
  • 2.5G Ethernet IP Core

    IP Core

    2.5G Ethernet IP Core

    The Lattice 2.5G Ethernet MAC + PHY IP core implements the Media Access Controller (MAC) and state machine functions for the Physical Coding Sub-layer (PCS) described in the IEEE 802.3 (1000BASE-X) specification.
    CertusPro-NX, Avant-G, Avant-X 
    Lattice Radiant, APB, Ethernet, PCS, IEEE 802.3, Ethernet Bundle 
  • SLVS-EC Receiver IP Core

    IP Core

    SLVS-EC Receiver IP Core

    The SLVS-EC RX IP provides the FPGA an interface to receive serial data from CMOS Image Sensors and offers a solution to convert the incoming serial data to a parallel pixel data format.
    CertusPro-NX 
    SLVS-EC, APB, AHB, AMBA, PMA, PCS, MPCS 
    SLVS-EC Receiver IP Core
  • Avant MPPHY Module

    Avant MPPHY Module

    The MPPHY Module supports the most common high-speed SERDES protocols used for inter-chip connectivity.
    Avant-G, Avant-X, Certus-N2 
    Lattice Avant, Lattice Radiant, PCS, PMA, SERDES 
    Avant MPPHY Module
  • PHY Interface for PCI Express - PIPE

    IP Core

    PHY Interface for PCI Express - PIPE

    A standard interface between a PHY device and the Media Access (MAC) layer for PCI Express (PCIe) applications
    LatticeECP3, LatticeECP2/M 
    PCIe, PCS, SERDES, Guidance Systems, Smart munitions 
    PHY Interface for PCI Express - PIPE
  • 10Gb Ethernet PCS IP Core

    IP Core

    10Gb Ethernet PCS IP Core

    The archived IP has been merged with the 10G Ethernet (MAC + PHY) IP Core.
    CertusPro-NX 
    Ethernet, APB, PCS 
    10Gb Ethernet PCS IP Core
  • sFPDP-Gen3 (VITA 17.3) IP Core

    IP Core

    sFPDP-Gen3 (VITA 17.3) IP Core

    High speed, low overhead serial protocol providing over 95% bandwidth efficiency. Our sFPDP-Gen3 IP (VITA 17.3) IP core can be configured for any transceiver line rate supported by the FPGA and can support any number of bonded channels for unprecendented bandwidth scalability.
    Avant-G, Avant-X 
    Data Communication, DSP, PCS, SERDES, Image Processing 
    sFPDP-Gen3 (VITA 17.3) IP Core
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