SLVS-EC Receiver IP Core

Scalable Low Voltage Signaling Embedded Clock Receiver IP Core

The SLVS-EC RX IP provides the FPGA an interface to receive serial data from CMOS Image Sensors and offers a solution to convert the incoming serial data to a parallel pixel data format. This can receive up to eight lanes of differential serial data running at a maximum of 5 Gbps per lane.

The SLVS-EC functions defined by the PHY Layer are supported by the Multi-Protocol PCS (MPCS) soft IP which instantiates the PMA/PCS IPs, and the Link Layer functions defined by the PHY Layer are supported.


  • Compliant with SLVS-EC Protocol specification v2.0
  • Back compatibility with SLVS-EC Protocol specification v1.2
  • Supports PHY layer functions using the embedded PMA/PCS in CertusPro-NX FPGA device
  • Supports up to eight lanes each running at a maximum of 5 Gbps baud rate
  • Supports AXI4-STREAM Protocol as a selectable option for data interface and AMBA 3 APB Protocol v1.0 for register access to control the IP

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Block Diagram

Resource Utilization

This table shows the configuration and resource utilization for LFCPNX-100-9BBG484C using LSE of Lattice Radiant software 3.0.
Configuration Clk Fmax (MHz)* Registers LUTs Programmable I/O DSPs sysMEM EBRS
4 Lanes
Baud Grade 3
FIFO Depth = 16
125 9964 26875 10 36 24

*Note: Fmax is generated when the FPGA design only contains SLVS-EC Rx IP and the target Frequency is 125 MHz. These values may be reduced when user logic is added to the FPGA design.

Ordering Information

Device Family Multi-site Perpetual Single Seat Annual


Quick Reference
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SLVS-EC Receiver IP Core - User Guide
FPGA-IPUG-02125 1.9 1/14/2024 PDF 1.3 MB

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