The Lattice Scalable Low Voltage Signaling-Embedded Clock Receiver (SLVS-EC Rx) IP core provides the FPGA an interface to receive serial data from CMOS Image Sensors and offers a solution to convert the incoming serial data to a parallel pixel data format. This can receive up to eight lanes of differential serial data running at a maximum of 5 Gbps per lane. The SLVS-EC functions defined by the PHY Layer are supported by the Multi-Protocol PCS (MPCS) soft IP which instantiates the PMA/PCS IPs, and the Link Layer functions defined by the PHY Layer are supported.
Resource Utilization details are available in the IP Core User Guide.
Features
- Compliant with SLVS-EC Protocol specification v2.0
- Back compatibility with SLVS-EC Protocol specification v1.2
- Supports PHY layer functions using the embedded PMA/PCS in CertusPro-NX FPGA device
- Supports up to eight lanes each running at a maximum of 5 Gbps baud rate
- Supports AXI4-STREAM Protocol as a selectable option for data interface and AMBA 3 APB Protocol v1.0 for register access to control the IP
