SLVS-EC Receiver IP Core

Scalable Low Voltage Signaling Embedded Clock Receiver IP Core

The SLVS-EC RX IP provides the FPGA an interface to receive serial data from CMOS Image Sensors and offers a solution to convert the incoming serial data to a parallel pixel data format. This can receive up to eight lanes of differential serial data running at a maximum of 5 Gbps per lane.

The SLVS-EC functions defined by the PHY Layer are supported by the Multi-Protocol PCS (MPCS) soft IP which instantiates the PMA/PCS IPs, and the Link Layer functions defined by the PHY Layer are supported.


  • Compliant with SLVS-EC Protocol specification v2.0
  • Back compatibility with SLVS-EC Protocol specification v1.2
  • Supports functions defined by PHY Layer using the embedded PMA/PCS in CertusPro-NX FPGA device, which has two channels of 6.25 Gbps serializer/deserializer with 8b10b encoding/decoding
  • Supports up to eight lanes each running at a maximum of 5 Gbps baud rate
  • Supports AXI4-STREAM Protocol as a selectable option for data interface and AMBA 3 APB Protocol v1.0 for register access to control the IP

Jump to

Block Diagram

Performance and Size

This table shows the configuration and resource utilization for LFCPNX-100-9BBG484C using LSE of Lattice Radiant software 3.0.
Configuration Clk Fmax (MHz)* Registers LUTs Programmable I/O DSPs sysMEM EBRS
4 Lanes
Baud Grade 3
FIFO Depth = 16
125 7596 26292 10 36 24

Ordering Information

Family License Type Ordering Part Number
CertusPro-NX Single-Design License SLVS-EC-RX-CPNX-U
Multi-Site License SLVS-EC-RX-CPNX-UT


标题 编号 版本 日期 格式 文件大小
SLVS-EC Receiver IP Core - Lattice Radiant Software
FPGA-IPUG-02125 1.3 6/23/2021 PDF 1.8 MB
Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.