Satellite Communications

Low power, reliable FPGAs for Communications

Satellite communication systems where bandwidth and power are at a premium are challenged to deliver higher bandwidth and more flexible connectivity in LEO constellations and beyond where radiation is a constant threat to electronics. Lattice FPGAs with inherent radiation resilience and embedded hardened error correction implement complex communication algorithms such as software defined radios and connectivity solutions with digital flexible payloads while withstanding radiation. 

  • Immunity to single event latch up and high Total Ionizing Dose resilience in presence of heavy ions
  • Novel configuration memory architecture significantly lowers multiple-bit upsets.
  • Mitigation techniques including built-in error detection and correction , sophisticated Triple Modular Redundancy and fault tolerant design techniques
  • Low power and compact packages enable novel distributed architectures deployed in small satellites

Features

  • Up to 1800 high performance DSP blocks and 1000 embedded memory blocks coupled with HDL programming flow accelerate development of novel signal processing algorithms.
  • Lowest soft error rate (SER) in its class and highest latch-up immunity coupled with built-in scrubber to maximize integrity of space systems.
  • Commercial-off-the-shelf (COTS) plastic components speed up prototype build and maintain same design for flight.
  • Complete satellite reference designs with ecosystem partners analog front end, thermal solutions and power delivery networks accelerate time to launch.

Jump to

Example Applications

Sensor Control

  • Bridge processor to sensors for distributed architectures
  • Small packages and soft RISC-V Cores for control / management
  • Embedded ADC and DAC blocks to simplify design and test 

Telemetry

  • Instant-on performance enable fast response and boot time requirements
  • In-orbit reconfiguration to future proof your design
  • Large on-chip memory for on-chip processing and storage 

Data Acquisition

  • Digital Signal Processing to offload SBC and accelerate complex functions
  • High speed Serdes simplifies design and supports multiple protocols
  • Vision interface and signal processing adapts to a variety of sensors

Reference Design

目标分类参考设计

Reference Design

目标分类参考设计

该参考设计展示了在网络边缘设备应用中实现基于机器学习的目标分类示例。
目标分类参考设计
SPI Slave 到 PWM 产生

Reference Design

ADC 接口

Reference Design

ADC 接口

Interfaces with the Texas Instruments (TI) ADS64XX family of ADCs via LatticeECP3 FPGA high-speed LVDS I/O
ADC 接口
ECC模块参考设计

Reference Design

ECC模块参考设计

Provides Single Error Correction - Double Error Detection (SECDED) capability based on a class of optimal minimum oddweight error parity codes
ECC模块参考设计

Demo

目标分类演示

演示

目标分类演示

该演示提供了在CertusPro-NX FPGA上运行的检测、分类和追踪多个目标的应用示例。
目标分类演示
莱迪思图像信号处理演示

演示

莱迪思图像信号处理演示

为嵌入式视觉开发套件提供基于ECP5 FPGA的完整ISP示例设计,非常适合工业、医疗和汽车应用。
莱迪思图像信号处理演示

IP Cores

Development Kits & Boards

Documentation

快速参考
资讯资源
标题 编号 版本 日期 格式 文件大小
选择全部
High Reliability & Functional Safety for FPGAs with Synplify & Radiant
WP0036 1.0 3/25/2024 PDF 2.3 MB
Lattice Avant SED/SEC User Guide
FPGA-TN-02290 0.82 6/9/2025 PDF 585.4 KB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 2.4 8/27/2025 PDF 1.4 MB
Thermal Management
FPGA-TN-02044 5.7 10/13/2025 PDF 1.1 MB
Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
FPGA-TN-02257 1.1 5/31/2022 PDF 1 MB
标题 编号 版本 日期 格式 文件大小
选择全部
Lattice Avant SED/SEC User Guide
FPGA-TN-02290 0.82 6/9/2025 PDF 585.4 KB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 2.4 8/27/2025 PDF 1.4 MB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-02041 5.1 8/5/2025 PDF 693.7 KB
Thermal Management
FPGA-TN-02044 5.7 10/13/2025 PDF 1.1 MB
Power Management and Calculation for Certus-NX, CertusPro-NX, and MachXO5-NX Devices
FPGA-TN-02257 1.1 5/31/2022 PDF 1 MB
标题 编号 版本 日期 格式 文件大小
选择全部
SEDC IP Module User Guide – Lattice Radiant Software
FPGA-IPUG-02066 1.2 6/23/2021 PDF 908.3 KB
标题 编号 版本 日期 格式 文件大小
选择全部
High Reliability & Functional Safety for FPGAs with Synplify & Radiant
WP0036 1.0 3/25/2024 PDF 2.3 MB