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  • Object Classification Demonstration

    Demo

    Object Classification Demonstration

    This object classification demo provides a sample application for detecting, classifying, and tracking multiple objects running on CertusPro-NX FPGA.
    Object Classification Demonstration
  • Object Classification Reference Design

    Reference Design

    Object Classification Reference Design

    The Object Classification reference design shows examples on implementing machine-learning based object classification to edge devices applications.
    Object Classification Reference Design
  • CertusPro-NX Voice and Vision Machine Learning Board

    Board

    CertusPro-NX Voice and Vision Machine Learning Board

    Design AI use cases for the Edge quickly! This board along with the Lattice sensAI solution stack provide the tools for developing vision and audio-based AI applications.
    CertusPro-NX Voice and Vision Machine Learning Board
  • CSI-2/DSI D-PHY Transmitter IP Core

    IP Core

  • Lattice Image Signal Processing Demo

    Demo

    Lattice Image Signal Processing Demo

    Provides a complete ISP example design on the Lattice ECP5 FPGA for the Embedded Vision Development Kit, ideal for Industrial, Medical, and Automotive applications.
    Lattice Image Signal Processing Demo
  • UART 16550 IP Core

    IP Core

    UART 16550 IP Core

    ​​Lattice UART16550 IP Core is designed for use in serial communication, supporting the RS-232, RS-422, RS-485, and Electronic Industries Association (EIA) standards, among others.​
    UART 16550 IP Core
  • Sensor Interfacing and Preprocessing

    Reference Design

    Sensor Interfacing and Preprocessing

    Aggregates data from multiple I2C interfaces and performs preprocessing like buffering, timestamping and complex event triggering based on data analysis.
    Sensor Interfacing and Preprocessing
  • SPI Slave to PWM Generation Reference Design

    Reference Design

    SPI Slave to PWM Generation Reference Design

    Sets the frequency and duty cycle of a PWM (Pulse-Width Modulator) using data from an external SPI master.
    SPI Slave to PWM Generation Reference Design
  • ADC Interface

    Reference Design

    ADC Interface

    Interfaces with the Texas Instruments (TI) ADS64XX family of ADCs via LatticeECP3 FPGA high-speed LVDS I/O
    ADC Interface
  • ECC Module Reference Design

    Reference Design

    ECC Module Reference Design

    Provides Single Error Correction - Double Error Detection (SECDED) capability based on a class of optimal minimum oddweight error parity codes
    ECC Module Reference Design
  • GRHSSL - High Speed Serial Link Controller IP Core

    IP Core

    GRHSSL - High Speed Serial Link Controller IP Core

    The GRHSSL IP is a highly configurable high-speed serial link controller, described in VHDL. It can implement a SpaceFibre controller, a WizardLink controller or both.
    GRHSSL - High Speed Serial Link Controller IP Core
  • GRPCI IP Core

    IP Core

    GRPCI IP Core

    The GRPCI IP core provides a 32-bit master/target interface for AMBA AHB 2.0 systems. It includes parameterizable FIFOs for both master and target operation and can optionally be provided with an independent DMA engine.
    GRPCI IP Core
  • GRSPW_CODEC SpaceWire Codec IP Core

    IP Core

    GRSPW_CODEC SpaceWire Codec IP Core

    The GRSPW_CODEC core implements a SpaceWire encoder decoder with a 9-bit wide FIFO host interface in each direction. The core complies to the SpaceWire standard (ECSS-E-ST-12C). Data is transmitted and received through FIFOs with configurable depth.
    GRSPW_CODEC SpaceWire Codec IP Core
  • GRSPW2 SpaceWire Link IP Core

    IP Core

    GRSPW2 SpaceWire Link IP Core

    The GRSPW2 implements a SpaceWire link controller with RMAP support and AMBA host interface. The core complies to the SpaceWire standard (ECSS-E-ST-50-12C) with the protocol identification extension (ECSS-E-ST-50-51C) and RMAP protocol (ECSS-E-ST-50-52C).
    GRSPW2 SpaceWire Link IP Core
  • NOEL-V RISC-V Processor IP Core

    IP Core

    NOEL-V RISC-V Processor IP Core

    The NOEL-V is a VHDL model of a processor that implements the RISC-V architecture, which can be configured to conform to the RV32 or RV64 architectures.
    NOEL-V RISC-V Processor IP Core
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