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  • Object Classification Demonstration

    Demo

    Object Classification Demonstration

    Sample demonstration for object detection, classification, and tracking multiple objects running on a low power general purpose FPGA using CNN Model
    Object Classification Demonstration
  • Object Classification Reference Design

    Reference Design

    Object Classification Reference Design

    A reference design for implementing object classification based on Mobilenet NN model running on Lattice CertusPro-NX low power FPGA
    Object Classification Reference Design
  • CertusPro-NX Voice and Vision Machine Learning Board

    Board

    CertusPro-NX Voice and Vision Machine Learning Board

    Design AI use cases for the Edge quickly! This board along with the Lattice sensAI solution stack provide the tools for developing vision and audio-based AI applications.
    CertusPro-NX Voice and Vision Machine Learning Board
  • Lattice Image Signal Processing Demo

    Demo

    Lattice Image Signal Processing Demo

    Provides a complete ISP example design on the Lattice ECP5 FPGA for the Embedded Vision Development Kit, ideal for Industrial, Medical, and Automotive applications.
    Lattice Image Signal Processing Demo
  • UART 16550 IP Core

    IP Core

    UART 16550 IP Core

    Configurable UART port. Compatible with PC16550D. 7 or 8 bit data width, 1, 1.5, 2 stop bits for Tx. Multiple parity and baud rate options.
    UART 16550 IP Core
  • Sensor Interfacing and Preprocessing

    Reference Design

    Sensor Interfacing and Preprocessing

    Aggregates data from multiple I2C interfaces and performs preprocessing like buffering, timestamping and complex event triggering based on data analysis.
    Sensor Interfacing and Preprocessing
  • SPI Slave to PWM Generation

    Reference Design

    SPI Slave to PWM Generation

    Sets the frequency and duty cycle of a PWM (Pulse-Width Modulator) using data from an external SPI master.
    SPI Slave to PWM Generation
  • ADC Interface

    Reference Design

    ADC Interface

    Interfaces with the Texas Instruments (TI) ADS64XX family of ADCs via LatticeECP3 FPGA high-speed LVDS I/O
    ADC Interface
  • ECC Module Reference Design

    Reference Design

    ECC Module Reference Design

    Provides Single Error Correction - Double Error Detection (SECDED) capability based on a class of optimal minimum oddweight error parity codes
    ECC Module Reference Design
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