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Lattice Solutions
Lattice Solutions
Everything you need to quickly and easily complete your design
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General Purpose
Includes all ECP
Video Connection
Includes all CrossLink
Ultra Low Power
Includes all iCE
Control & Security
Includes all MachXO
IP Cores
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Reference Designs
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View All
Narrow Your Results
Solution Type
Boards (2)
Demos
IP Cores (5)
Reference Designs (3)
Device Support
Certus-NX (1)
CertusPro-NX (1)
CrossLink-NX (1)
ispMACH 4000ZE (1)
LatticeECP2/M (4)
LatticeECP3 (7)
LatticeSC/M (2)
LatticeXP2 (8)
MachXO (5)
MachXO2 (2)
MachXO5-NX (1)
Tags
AHB (1)
AHB-Lite (1)
APB (1)
Automotive (1)
Bus Controllers (7)
DDR SDRAM (2)
Defense (2)
PCI (10)
PCIe (1)
PCIe IP Suite (4)
RTL (1)
SERDES (1)
Wishbone (1)
Providers
Lattice (10)
Clear All
IP Core
PCI Express x1 & x4 IP Core for Nexus-based FPGAs
The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
CrossLink-NX
,
Certus-NX
,
CertusPro-NX
,
MachXO5-NX
APB
,
AHB
,
AHB-Lite
,
RTL
,
PCI
,
PCIe
,
Bus Controllers
,
Defense
,
Automotive
IP Core
32 Bit PCI Master/Target
Provides a customizable 32/64-bit master/target or target solution - revision 2.2 for speeds up to 66MHz
LatticeECP2/M
,
MachXO
,
LatticeXP2
,
LatticeECP3
,
MachXO2
Bus Controllers
,
PCI
,
PCIe IP Suite
IP Core
32 Bit PCI Target
Fully compliant with the PCI Local Bus Specification, revision 2.2 for speeds up to 66MHz
LatticeECP2/M
,
MachXO
,
LatticeXP2
,
LatticeECP3
,
MachXO2
Bus Controllers
,
PCI
,
PCIe IP Suite
IP Core
64 Bit PCI Master/Target
Fully compliant with the PCI SIG 3.0 for speeds up to 66MHz. Customizable for 32/64-bit master/target or target solution
LatticeSC/M
,
LatticeECP2/M
,
LatticeXP2
,
LatticeECP3
Bus Controllers
,
PCI
,
PCIe IP Suite
IP Core
64 Bit PCI Target
Fully compliant with the PCI SIG 3.0 for speeds up to 66MHz. Customizable for 32/64-bit.
LatticeSC/M
,
LatticeECP2/M
,
LatticeXP2
,
LatticeECP3
Bus Controllers
,
PCI
,
PCIe IP Suite
Reference Design
PCI Target 32-bit/33MHz
Fully Compliant with PCI 2.2 specification.
ispMACH 4000ZE
,
MachXO
,
LatticeXP2
,
LatticeECP3
Bus Controllers
,
PCI
,
Defense
Reference Design
PCI to NOR Flash Interface
Provides an interface between the CPU with PCI initiator interface and a NOR-type Flash memory
LatticeXP2
,
MachXO
Bus Controllers
,
PCI
Reference Design
PCI/WISHBONE Bridge
Provides a bridge between the Lattice PCI Target 32-bit/33MHz Reference Design and a WISHBONE slave device.
MachXO
,
LatticeXP2
,
LatticeECP3
PCI
,
Wishbone
Board
LatticeECP3 Serial Protocol Evaluation Board
No longer available - for reference only. Allows designers to investigate and experiment with the LatticeECP3 high-speed SERDES transceivers.
LatticeECP3
DDR SDRAM
,
PCI
,
SERDES
Board
LatticeXP2 Advanced Evaluation Board
No longer available - for reference only. General purpose evaluation platform for the LatticeXP2 FPGA (XP2-17) + DDR2 SDRAM SO-DIMM socket (32-bit).
LatticeXP2
DDR SDRAM
,
PCI
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