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  • PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    IP Core

    PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 
    APB, AHB, AHB-Lite, RTL, PCI, PCIe, Bus Controllers, Defense, Automotive 
    PCI Express x1 & x4 IP Core for Nexus-based FPGAs
  • 32 Bit PCI Master/Target

    IP Core

    32 Bit PCI Master/Target

    Provides a customizable 32/64-bit master/target or target solution - revision 2.2 for speeds up to 66MHz
    LatticeECP2/M, MachXO, LatticeXP2, LatticeECP3, MachXO2 
    Bus Controllers, PCI, PCIe IP Suite 
    32 Bit PCI Master/Target
  • 32 Bit PCI Target

    IP Core

    32 Bit PCI Target

    Fully compliant with the PCI Local Bus Specification, revision 2.2 for speeds up to 66MHz
    LatticeECP2/M, MachXO, LatticeXP2, LatticeECP3, MachXO2 
    Bus Controllers, PCI, PCIe IP Suite 
    32 Bit PCI Target
  • 64 Bit PCI Master/Target

    IP Core

    64 Bit PCI Master/Target

    Fully compliant with the PCI SIG 3.0 for speeds up to 66MHz. Customizable for 32/64-bit master/target or target solution
    LatticeSC/M, LatticeECP2/M, LatticeXP2, LatticeECP3 
    Bus Controllers, PCI, PCIe IP Suite 
    64 Bit PCI Master/Target
  • 64 Bit PCI Target

    IP Core

    64 Bit PCI Target

    Fully compliant with the PCI SIG 3.0 for speeds up to 66MHz. Customizable for 32/64-bit.
    LatticeSC/M, LatticeECP2/M, LatticeXP2, LatticeECP3 
    Bus Controllers, PCI, PCIe IP Suite 
    64 Bit PCI Target
  • PCI Target 32-bit/33MHz

    Reference Design

    PCI Target 32-bit/33MHz

    Fully Compliant with PCI 2.2 specification.
    ispMACH 4000ZE, MachXO, LatticeXP2, LatticeECP3 
    Bus Controllers, PCI, Defense 
    PCI Target 32-bit/33MHz
  • PCI to NOR Flash Interface

    Reference Design

    PCI to NOR Flash Interface

    Provides an interface between the CPU with PCI initiator interface and a NOR-type Flash memory
    LatticeXP2, MachXO 
    Bus Controllers, PCI 
    PCI to NOR Flash Interface
  • PCI/WISHBONE Bridge

    Reference Design

    PCI/WISHBONE Bridge

    Provides a bridge between the Lattice PCI Target 32-bit/33MHz Reference Design and a WISHBONE slave device.
    MachXO, LatticeXP2, LatticeECP3 
    PCI, Wishbone 
    PCI/WISHBONE Bridge
  • LatticeECP3 Serial Protocol Evaluation Board

    Board

    LatticeECP3 Serial Protocol Evaluation Board

    No longer available - for reference only. Allows designers to investigate and experiment with the LatticeECP3 high-speed SERDES transceivers.
    LatticeECP3 
    DDR SDRAM, PCI, SERDES 
    LatticeECP3 Serial Protocol Evaluation Board
  • LatticeXP2 Advanced Evaluation Board

    Board

    LatticeXP2 Advanced Evaluation Board

    No longer available - for reference only. General purpose evaluation platform for the LatticeXP2 FPGA (XP2-17) + DDR2 SDRAM SO-DIMM socket (32-bit).
    LatticeXP2 
    DDR SDRAM, PCI 
    LatticeXP2 Advanced Evaluation Board
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