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  • PCI Express for Avant FPGAs

    IP Core

    PCI Express for Avant FPGAs

    The Lattice PCIe X8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express for Avant FPGAs
  • PCI Express for Nexus FPGAs

    IP Core

    PCI Express for Nexus FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express for Nexus FPGAs
  • 32 Bit PCI Master/Target

    IP Core

    32 Bit PCI Master/Target

    Provides a customizable 32/64-bit master/target or target solution - revision 2.2 for speeds up to 66MHz
    32 Bit PCI Master/Target
  • 32 Bit PCI Target

    IP Core

    32 Bit PCI Target

    Fully compliant with the PCI Local Bus Specification, revision 2.2 for speeds up to 66MHz
    32 Bit PCI Target
  • 64 Bit PCI Master/Target

    IP Core

    64 Bit PCI Master/Target

    Fully compliant with the PCI SIG 3.0 for speeds up to 66MHz. Customizable for 32/64-bit master/target or target solution
    64 Bit PCI Master/Target
  • 64 Bit PCI Target

    IP Core

    64 Bit PCI Target

    Fully compliant with the PCI SIG 3.0 for speeds up to 66MHz. Customizable for 32/64-bit.
    64 Bit PCI Target
  • PCI Target 32-bit/33MHz

    Reference Design

    PCI Target 32-bit/33MHz

    Fully Compliant with PCI 2.2 specification.
    PCI Target 32-bit/33MHz
  • PCI to NOR Flash Interface

    Reference Design

    PCI to NOR Flash Interface

    Provides an interface between the CPU with PCI initiator interface and a NOR-type Flash memory
    PCI to NOR Flash Interface
  • PCI/WISHBONE Bridge Reference Design

    Reference Design

    PCI/WISHBONE Bridge Reference Design

    Provides a bridge between the Lattice PCI Target 32-bit/33MHz Reference Design and a WISHBONE slave device.
    PCI/WISHBONE Bridge Reference Design
  • GRPCI IP Core

    IP Core

    GRPCI IP Core

    The GRPCI IP core provides a 32-bit master/target interface for AMBA AHB 2.0 systems. It includes parameterizable FIFOs for both master and target operation and can optionally be provided with an independent DMA engine.
    GRPCI IP Core
  • LatticeECP3 Serial Protocol Evaluation Board

    Board

    LatticeECP3 Serial Protocol Evaluation Board

    No longer available - for reference only. Allows designers to investigate and experiment with the LatticeECP3 high-speed SERDES transceivers.
    LatticeECP3 Serial Protocol Evaluation Board
  • LatticeXP2 Advanced Evaluation Board

    Board

    LatticeXP2 Advanced Evaluation Board

    No longer available - for reference only. General purpose evaluation platform for the LatticeXP2 FPGA (XP2-17) + DDR2 SDRAM SO-DIMM socket (32-bit).
    LatticeXP2 Advanced Evaluation Board
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