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  • 8N1 UART Transceiver Reference Design

    Reference Design

    8N1 UART Transceiver Reference Design

    8-bit data, no parity, and 1 stop bit Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel and parallel to serial conversions on data characters received from a peripheral device or CPU
    8N1 UART Transceiver Reference Design
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    The RISC-V SM CPU IP processes data and instructions while considering the external interrupts. The CPU core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • Soft I2C Bus Master

    Reference Design

    Soft I2C Bus Master

    Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families
    Soft I2C Bus Master
  • Soft I2C Slave Peripheral

    Reference Design

    Soft I2C Slave Peripheral

    Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families
    Soft I2C Slave Peripheral
  • LXO2000

    Board

    LXO2000

    The TEL0001 "LXO2000" is a low cost FPGA module integrating a Lattice XO2-4000 and on-board USB/JTAG. It's compatible to the Arduino MKR standard.
    LXO2000
  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C Bus Master
  • I2C Master - WISHBONE Compatible

    Reference Design

    I2C Master - WISHBONE Compatible

    Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus
    I2C Master - WISHBONE Compatible
  • MachXO2 Breakout Board

    Board

    MachXO2 Breakout Board

    A simple low-cost board that provides complete I/O access to the MachXO2 plus LEDs, Prototyping Area Power and Programming on-board.
    MachXO2 Breakout Board
  • Simple Sigma-Delta ADC

    Reference Design

    Simple Sigma-Delta ADC

    Implements an Analog-to-Digital (ADC) using on-FPGA differntial LVDS inputs (or inexpensive analog comparitor). Save cost by eliminating external ADC devices.
    Simple Sigma-Delta ADC
  • SPI Slave to PWM Generation

    Reference Design

    SPI Slave to PWM Generation

    Sets the frequency and duty cycle of a PWM (Pulse-Width Modulator) using data from an external SPI master.
    SPI Slave to PWM Generation
  • MachXO2 I2C Embedded Programming Access Firmware

    Reference Design

    MachXO2 I2C Embedded Programming Access Firmware

    Provides C code for interfacing to MachXO2 from a microcontroller, and RTL for implementing I2C between an external master and the MachXO2
    MachXO2 I2C Embedded Programming Access Firmware
  • Local Interconnect Network (LIN) Cast Core

    IP Core

    Local Interconnect Network (LIN) Cast Core

    Transmits and receives complete LIN frames to perform serial communication according to the LIN protocol specification
    LIN 
    Local Interconnect Network (LIN) Cast Core
  • UART Reference Design - WISHBONE Compatible

    Reference Design

    UART Reference Design - WISHBONE Compatible

    UART (Universal Asynchronous Receiver/Transmitter) provides both Rx and Tx between the WISHBONE system bus and an RS232 serial communication channel.
    UART Reference Design - WISHBONE Compatible
  • SDR SDRAM Controller-Advanced Reference Design

    Reference Design

    SDR SDRAM Controller-Advanced Reference Design

    Provides a simple generic system interface to the bus master, reducing the user's effort to deal with the SDRAM command interface.
    SDR SDRAM Controller-Advanced Reference Design
  • CAN-CTRL

    IP Core

    CAN-CTRL

    Compliant to CAN 2.0 and CAN FD (ISO 11898-1.2015). Similar to Philips SJA1000 - error analysis, diagnosis, system maintenance, and optimization features.
    CAN-CTRL
  • AK-MACHXO2-7000 Development Board

    Board

    AK-MACHXO2-7000 Development Board

    Low-cost development platform featuring the MachXO2-7000 FPGA, Ethernet, SDRAM, microSD, serial flash, UART, VGA output and an embedded JTAG programmer
    AK-MACHXO2-7000 Development Board
  • Cyclic Redundancy Check

    Reference Design

    Cyclic Redundancy Check

    Implements CRC generator and checker with polynomial orders from CRC-1 to CRC-64
    Cyclic Redundancy Check
  • STEP-MXO2 Development Board

    Board

    STEP-MXO2 Development Board

    A small, breadboard friendly 40-pin DIP form factor board build around Lattice MachXO2. Available in China only.
    STEP-MXO2 Development Board
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