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  • USB 2.0 Device with FIFO Interface (USB20HF)

    IP Core

    USB 2.0 Device with FIFO Interface (USB20HF)

    USB20HF IP Core provides FIFO & ULPI interface. It supports High Speed and Full Speed functionality for 15 IN/OUT endpoints.
    USB 2.0 Device with FIFO Interface (USB20HF)
  • 8N1 UART Transceiver Reference Design

    Reference Design

    8N1 UART Transceiver Reference Design

    8-bit data, no parity, and 1 stop bit Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel and parallel to serial conversions on data characters received from a peripheral device or CPU
    8N1 UART Transceiver Reference Design
  • MachXO2ZE Breakout Board

    Board

    MachXO2ZE Breakout Board

    MachXO2ZE Breakout Board, a development board that uses a powerful FPGA with embedded system security to help you design and innovate your next great idea or product.
    MachXO2ZE Breakout Board
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    The RISC-V SM CPU IP processes data and instructions while considering the external interrupts. The CPU core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • Soft I2C Bus Master

    Reference Design

    Soft I2C Bus Master

    Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families
    Soft I2C Bus Master
  • Soft I2C Slave Peripheral

    Reference Design

    Soft I2C Slave Peripheral

    Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families
    Soft I2C Slave Peripheral
  • LXO2000

    Board

    LXO2000

    The TEL0001 "LXO2000" is a low cost FPGA module integrating a Lattice XO2-4000 and on-board USB/JTAG. It's compatible to the Arduino MKR standard.
    LXO2000
  • Generic Soft SPI Master Controller Demonstration

    Demo

    Generic Soft SPI Master Controller Demonstration

    This demo implements the Generic Soft SPI Master Controller Reference Design by performing simple transactions to the external SPI Flash device found in the MachXO3-9400 Development Board
    Generic Soft SPI Master Controller Demonstration
  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C Bus Master
  • I2C Master - WISHBONE Compatible

    Reference Design

    I2C Master - WISHBONE Compatible

    Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus
    I2C Master - WISHBONE Compatible
  • I3C-S-MIPI-I3C-Basic-Slave-Controller

    IP Core

    I3C-S-MIPI-I3C-Basic-Slave-Controller

    Highly featured, SDR-Capable and HDR-Tolerant Slave controller. Supports hot-join, in-band interrupts, & dynamic addressing. Works to any Lattice FPGA device.
    I3C-S-MIPI-I3C-Basic-Slave-Controller
  • JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder

    IP Core

    JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder

    Scalable, ultra-high throughput 8/12-bit JPEG decoder. Ideal for low-latency motion-Jpeg streaming. Full-HD or Ultra-HD capable depending on the device.
    JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder
  • JPEG-DX-S - Baseline and Extended JPEG Decoder

    IP Core

    JPEG-DX-S - Baseline and Extended JPEG Decoder

    Compact, 8bit and 12bit per color, JPEG decoder. Ideal for low-latency motion-Jpeg streaming.
    JPEG-DX-S - Baseline and Extended JPEG Decoder
  • JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder

    IP Core

    JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder

    Scalable, ultra-high throughput 8/12-bit encoder. Highly configurable with advanced bit-rate control. Ideal for low-latency motion-Jpeg streaming.
    JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder
  • JPEG-EX-S - Baseline and Extended JPEG Encoder

    IP Core

    JPEG-EX-S - Baseline and Extended JPEG Encoder

    Compact, 8bit and 12bit per color, JPEG encoder. Highly configurable with advanced bit-rate control features. Ideal for low-latency motion-Jpeg streaming.
    JPEG-EX-S - Baseline and Extended JPEG Encoder
  • SPMI-CTRL - MIPI SPMI Master or Slave Controller

    IP Core

    SPMI-CTRL - MIPI SPMI Master or Slave Controller

    Highly featured, easy-to-use master or slave controller supporting the latest version of the MIPI-SPMI specification. Portable to any Lattice FPGA device
    SPMI-CTRL - MIPI SPMI Master or Slave Controller
  • TSN-EP – TSN Ethernet Endpoint Controller

    IP Core

    TSN-EP – TSN Ethernet Endpoint Controller

    Highly flexible core supports timing synchronization (IEEE 802.1AS), traffic shaping (IEEE 802.1Qav, Qbv) and frame-preemption (IEEE 802.1Qbu, & 802.3br).
    TSN-EP – TSN Ethernet Endpoint Controller
  • UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack

    IP Core

    UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack

    Standalone, processor-less operation with up to 32 Rx and 32 Tx channels. Supports DHCP, IGMP, ICMP, ARP with cache, Jumbo and super Jumbo IPv4 frames.
    UDPIP-1G – 1Gbps UDP/IP Hardware Protocol Stack
  • MachXO2 Breakout Board

    Board

    MachXO2 Breakout Board

    A simple low-cost board that provides complete I/O access to the MachXO2 plus LEDs, Prototyping Area Power and Programming on-board.
    MachXO2 Breakout Board
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