The Lattice Semiconductor APB Interconnect Module is a fully parameterized soft IP for low latency interconnect fabric for APB system. It can be used to connect one or more APB bus master to one or more APB bus slave. Master-side arbitration is implemented within the module to minimize resource utilization.
The APB Interconnect Module supports round-robin based and fixed priority-based arbitration when multiple bus masters access the same slave port. The arbitration completes in one clock cycle, which means that the transaction is delayed by one clock cycle when arbitration occurs.
The design is implemented in Verilog HDL. The IP can be configured and generated using Lattice Propel Builder software. It can be targeted to MachXO3D FPGA devices and implemented using the Lattice Diamond software Place and Route tool integrated with the Synplify Pro synthesis tool.