In-Vehicle Infotainment

Reliable, Secure, Low Power FPGA for IVI Applications

With increasing adoption of mobile-influenced technologies in the modern cars, consumers are expecting smart phone features and functionalities in their car infotainment systems. Lattice’s auto grade FPGAs provide flexible, reliable, safe, and secure integration for In-Vehicle Infotainment (IVI) at lowest power.

  • Enabling low latency multi-sensor interfaces with image processing for realtime information for around vehicle driver awareness
  • Enabling flexible display process and connectivity using DisplayPort and image enhancement algorithms e.g., local dimming and video scaling levering the Lattice Drive™ Solution Stack
  • Enabling multitude of sensor and display interfaces with smart Human Machine Interface (HMI) using Lattice’s sensAI for In-Vehicle Infotainment systems
  • Enabling reliable, safe, and secure hardware authentication to protect against cyber-attacks while ensuring safety using Lattice FPGA’s hardware-based security and Functional Safety (FuSa)
IVI

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Block Diagram

Infotainment Systems Overview

Example Use Cases

Video Interface Bridge for In-Vehicle Infotainment systems

  • Interoperability between SoC and different displays
  • Offloads video image enhancement e.g., local dimming from SoC
  • Flexible video & image resolution and interface support
  • Flexible fabric allows end customer adjustments

Sensor Fusion & Aggregation over MIPI SERDES using CrossLink-NX

  • Up to 14 sensor aggregation with virtual channel support
  • Large on-chip memory for the faster frame and edge processing
  • Up to 10Gbps MIPI CSI-2 support for interface with MIPI SERDES technologies
  • Low power device with smaller footprint and security

E-Mirror Application using CrossLink-NX, ECP5, or LatticeXP2 FPGA

  • The camera sensor and Display interface support
  • Low power consumption for better thermals
  • Single-chip sensor aggregation and ISP solution
  • Promotes driver safety with better blind spot detection and night vision

Sensor aggregation with transmission up to 10m

  • Real-time image and data transfer using Auto SERDES chipsets
  • Sensor aggregation and fast data transfer without skew
  • Longer and cheaper wiring with low EMI
  • Heterogeneous sensor interfaces with FPGAs

Full-Featured ISP Pipeline for CrossLink-NX and ECP5

  • Full functional universal Image Signal Processing pipeline
  • User-configurable parametrizable IP
  • An image sensor interface independent with support for High Dynamic Range (HDR)
  • Optimized Lattice FPGA architecture

Driver Display overlay using CrossLink-NX and ECP5

  • Flexibility to support multiple display interfaces, like DSI, eDP
  • Display processor functionality that is configurable
  • Overlay capability of driver notifications at low power solution for better thermals

Hardware-based SecureBoot and Supply Chain Security

  • NIST compliant Platform Firmware Resiliency (PFR) for ADAS/ DA Domain Controllers
  • Real-time Protect, Detect and Recover for non-bypassable security to cover vulnerable attack points
  • Scalable solution with nanosecond level response for all firmware on the board

Chain of Trust Implementation for Automotive ECUs

  • Hardware Root-of-Trust is the first link in chain of trust that protects entire car system and ECUs
  • Hardened device configuration engine cryptographically authenticates MachXO3D’s configuration image at power-on
  • Embedded security block provides cryptographic functions to authenticate other platform firmware at for the Automotive ECU power-on
  • With instant-on capability MachXO3D is the first device to boot up securely on the platform and as such is an excellent anchor for Chain of Trust

360° Surround View using CrossLink-NX or ECP5 FPGA

  • 360° Surround-view monitoring system
  • Single-chip 4 camera aggregation & ISP solution
  • Interface to different camera sensors and display devices
  • Low latency and future proof

Reference Designs

MIPI CSI-2 to HDMI Reference Design

Reference Design

MIPI CSI-2 to HDMI Reference Design

MIPI CSI-2 to HDMI Reference Design includes the synthesizable MIPI-HDMI core design & stimulus generators, checkers, & a testbench necessary to simulate the design
MIPI CSI-2 to HDMI Reference Design
DisplayPort & Video Scaler Reference Design

Reference Design

DisplayPort & Video Scaler Reference Design

The Lattice Drive DisplayPort & Video Scaler Reference Design implements easy evaluation of various DisplayPort interface.
DisplayPort & Video Scaler Reference Design
Lattice mVision MIPI Video Sensor to PCIe Bridge Reference Design

Reference Design

Lattice mVision MIPI Video Sensor to PCIe Bridge Reference Design

Reference Design that shows transfer of sensor data to the computer memory and rendering of the data as video on the computer screen using the software driver.
Lattice mVision MIPI Video Sensor to PCIe Bridge Reference Design
SLVS-EC Sensor to PCIe Bridge Reference Design

Reference Design

SLVS-EC Sensor to PCIe Bridge Reference Design

SLVS-EC to PCIe reference design allows the quick interface to receive serial data from CMOS Image Sensors & convert to DMA/PCIe Subsystem data format.
SLVS-EC Sensor to PCIe Bridge Reference Design
CertusPro-NX N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

Reference Design

CertusPro-NX N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

Modular MIPI/D-PHY Reference Design - Multiple channel image data concatenated horizontally line by line and offers up to eight-channel aggregation.
CertusPro-NX N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

Demos

Lattice Image Signal Processing Demo

Demo

Lattice Image Signal Processing Demo

Provides a complete ISP example design on the Lattice ECP5 FPGA for the Embedded Vision Development Kit, ideal for Industrial, Medical, and Automotive applications.
Lattice Image Signal Processing Demo
Driver Monitoring System (DMS) Demonstration

Demo

Driver Monitoring System (DMS) Demonstration

The Driver Monitoring System Solution Demonstration highlights the capabilities of the newly introduced features of the Lattice Drive Solution Stack.
Driver Monitoring System (DMS) Demonstration
Lattice mVision DisplayPort to PCIe Demonstration

Demo

Lattice mVision DisplayPort to PCIe Demonstration

DisplayPort to PCIe bridge design demonstrates the functionality of transferring DisplayPort video data to a computer through PCIe with a DMA engine.
Lattice mVision DisplayPort to PCIe Demonstration
Lattice mVision MIPI DSI to DisplayPort Demonstration

Demo

Lattice mVision MIPI DSI to DisplayPort Demonstration

The MIPI Display Serial Interface (DSI) to DisplayPort (DP) bridge design features a MIPI D-PHY receiver front-end configuration with four lanes.
Lattice mVision MIPI DSI to DisplayPort Demonstration
MIPI CSI-2 to HDMI Demonstration

Demo

MIPI CSI-2 to HDMI Demonstration

Lattice MIPI-HDMI Demonstration is built using multiple Lattice IPs and some additional glue logic necessary to connect the IPs in a processing pipeline.
MIPI CSI-2 to HDMI Demonstration

IP Cores

Image Signal Processing IP Cores Suite

IP Core

Image Signal Processing IP Cores Suite

The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
Image Signal Processing IP Cores Suite
DisplayPort IP Core

IP Core

DisplayPort IP Core

The Lattice DisplayPort IP Core is designed for transmission and reception of serial-digital video for consumer and professional displays.
DisplayPort IP Core
Video Scaler IP Core

IP Core

Video Scaler IP Core

The Lattice Video Scaler IP Core is used to scale up or scale down the resolution of a video stream.
Video Scaler IP Core
Helion IONOS Image Signal Processing IP Portfolio

IP Core

Helion IONOS Image Signal Processing IP Portfolio

Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.
Helion IONOS Image Signal Processing IP Portfolio

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Support

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