In-Vehicle Infotainment

Reliable, Secure, Low Power FPGA for IVI Applications

With increasing adoption of mobile-influenced technologies in the modern cars, consumers are expecting smart phone features and functionalities in their car infotainment systems. Lattice’s auto grade FPGAs provide flexible, reliable, safe, and secure integration for In-Vehicle Infotainment (IVI) at lowest power.

  • Enabling low latency multi-sensor interfaces with image processing for realtime information for around vehicle driver awareness
  • Enabling multitude of sensor and display interfaces with smart Human Machine Interface (HMI) using Lattice’s sensAI for In-Vehicle Infotainment systems
  • Enabling reliable, safe, and secure hardware authentication to protect against cyber-attacks while ensuring safety using Lattice FPGA’s hardware-based security and Functional Safety (FuSa)
IVI

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Block Diagram

Infotainment Systems Overview

Example Use Cases

Sensor Fusion & Aggregation over MIPI SERDES using CrossLink-NX

  • Up to 14 sensor aggregation with virtual channel support
  • Large on-chip memory for the faster frame and edge processing
  • Up to 10Gbps MIPI CSI-2 support for interface with MIPI SERDES technologies
  • Low power device with smaller footprint and security

E-Mirror Application using CrossLink-NX, ECP5, or LatticeXP2 FPGA

  • The camera sensor and Display interface support
  • Low power consumption for better thermals
  • Single-chip sensor aggregation and ISP solution
  • Promotes driver safety with better blind spot detection and night vision

Sensor aggregation with transmission up to 10m

  • Real-time image and data transfer using Auto SERDES chipsets
  • Sensor aggregation and fast data transfer without skew
  • Longer and cheaper wiring with low EMI
  • Heterogeneous sensor interfaces with FPGAs

Full-Featured ISP Pipeline for CrossLink-NX and ECP5

  • Full functional universal Image Signal Processing pipeline
  • User-configurable parametrizable IP
  • An image sensor interface independent with support for High Dynamic Range (HDR)
  • Optimized Lattice FPGA architecture

Driver Display overlay using CrossLink-NX and ECP5

  • Flexibility to support multiple display interfaces, like DSI, eDP
  • Display processor functionality that is configurable
  • Overlay capability of driver notifications at low power solution for better thermals

Hardware-based SecureBoot and Supply Chain Security

  • NIST compliant Platform Firmware Resiliency (PFR) for ADAS/ DA Domain Controllers
  • Real-time Protect, Detect and Recover for non-bypassable security to cover vulnerable attack points
  • Scalable solution with nanosecond level response for all firmware on the board

Chain of Trust Implementation for Automotive ECUs

  • Hardware Root-of-Trust is the first link in chain of trust that protects entire car system and ECUs
  • Hardened device configuration engine cryptographically authenticates MachXO3D’s configuration image at power-on
  • Embedded security block provides cryptographic functions to authenticate other platform firmware at for the Automotive ECU power-on
  • With instant-on capability MachXO3D is the first device to boot up securely on the platform and as such is an excellent anchor for Chain of Trust

360° Surround View using CrossLink-NX or ECP5 FPGA

  • 360° Surround-view monitoring system
  • Single-chip 4 camera aggregation & ISP solution
  • Interface to different camera sensors and display devices
  • Low latency and future proof

Reference Designs

Lattice Image Signal Processing Reference Design

Reference Design

Lattice Image Signal Processing Reference Design

Configure an ECP5 FPGA-based ISP solution tailored to your Industrial, Medical, and Automotive application.
Lattice Image Signal Processing Reference Design
MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge for CertusPro-NX

Reference Design

MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge for CertusPro-NX

Modular MIPI/D-PHY Reference Design - MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge reference design takes DSI or CSI-2 MIPI data and converts them to OpenLDI format on LVDS.
MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge for CertusPro-NX
N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation with CertusPro-NX

Reference Design

N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation with CertusPro-NX

Modular MIPI/D-PHY Reference Design - Multiple channel image data concatenated horizontally line by line and offers up to eight-channel aggregation.
N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation with CertusPro-NX
SLVS-EC to MIPI CSI-2 with CertusPro-NX

Reference Design

SLVS-EC to MIPI CSI-2 with CertusPro-NX

Modular MIPI/D-PHY Reference Design - Support advance camera and display interconnections in mobile devices that enable higher performance sensor with optimized power.
SLVS-EC to MIPI CSI-2 with CertusPro-NX
SubLVDS to MIPI CSI-2 Image Sensor Bridge with CertusPro-NX

Reference Design

SubLVDS to MIPI CSI-2 Image Sensor Bridge with CertusPro-NX

Modular MIPI/D-PHY Reference Design - Solves the mismatch between SubLVDS output image sensor and an ISP/AP using CSI-2 interface.
SubLVDS to MIPI CSI-2 Image Sensor Bridge with CertusPro-NX

Demos

CSI-2 PCIe Bridge Demonstration

Demo

CSI-2 PCIe Bridge Demonstration

This design demonstrates the functionality of transferring MIPI CSI-2 camera video data to computer via PCIe with a Direct Memory Access (DMA) engine.
CSI-2 PCIe Bridge Demonstration
Lattice Image Signal Processing Demo

Demo

Lattice Image Signal Processing Demo

Provides a complete ISP example design on the Lattice ECP5 FPGA for the Embedded Vision Development Kit, ideal for Industrial, Medical, and Automotive applications.
Lattice Image Signal Processing Demo
SLVS-EC to HDMI Demo for CertusPro-NX

Demo

SLVS-EC to HDMI Demo for CertusPro-NX

The single camera SLVS-EC to HDMI demonstration uses IMX535 image sensor to output 1080p video and extracts the video pixels which is then displayed on HDMI.
SLVS-EC to HDMI Demo for CertusPro-NX
DisplayPort Receive Demo

Demo

DisplayPort Receive Demo

Uses Bitec's DisplayPort IP core on the ECP5 FPGA in Lattice's Embedded Vision Development Kit. Compliant with DisplayPort 1.4a (including eDP 1.4 support).
DisplayPort Receive Demo

IP Cores

Helion IONOS Image Signal Processing IP Portfolio

IP Core

Helion IONOS Image Signal Processing IP Portfolio

Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.
Helion IONOS Image Signal Processing IP Portfolio
CSI-2/DSI D-PHY Receiver

IP Core

FPD-LINK Receiver

IP Core

FPD-LINK Receiver

Modular MIPI/D-PHY IP - Converts FPD-LINK Video Streams to Pixel Clock Domain
FPD-LINK Receiver

Automotive Quality & Safety Standard

Support

Technical Support

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Quality & Reliability

Reference Material to Help Answer Your Questions

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