MIPI CSI/DSI IP Core

Flexible MIPI Solution for High-Speed, Low-Power Video Transmission in FPGAs

Related Products

The Lattice™ MIPI® CSI/DSI IP provides a flexible solution for transmission and reception of high-speed video data over a Mobile Industry Processor Interface (MIPI)-compatible D-PHY interface in FPGA designs. MIPI enables high-speed, low-power video transmission between components like cameras and displays, and is widely used in smartphones, automotive systems, industrial equipment, and IoT devices.

Features

  • Supports MIPI D-PHY with 1, 2, or 4 data lanes and 1 clock lane.
  • Supports Soft D‑PHY bandwidth up to 1.5 Gbps per lane, for a total bandwidth of 6 Gbps
  • Supports continuous and non‑continuous MIPI D‑PHY clock operation
  • MIPI CSI/DSI IP on Transmitter Mode
    • Supports MIPI CSI‑2
    • Supports 1, 2, and 4 pixels per clock (PPC)
  • MIPI CSI/DSI IP on Receiver Mode
    • Supports MIPI CSI‑2 and DSI‑2
    • Supports 1, 2, and 4 pixels per clock

 

Feature / Aspect Legacy CSI/DSI D-PHY Receiver and Transmitter IP Core New MIPI CSI/DSI IP Core
What it Implements? PHY to Packetizer/Depacketizer layer: receives/transmits CSI/DSI; optional packet processing, stays in byte domain PHY to Pixel layer: receives/transmits CSI/DSI, translates to UVSI (AXI4 Stream pixel domain
Input/Output Data Interface Parallel byte data (8/16/32/64 bit) UVSI video stream (AXI4 Stream compliant RGB/RAW pixel domain)
Video Format Handling Video format handling not part of IP; only passes CSI/DSI payload (protocol decode optional) Supports RGB888, RGB565, RAW10, RAW12
Directional Control Separate Rx and Tx IP cores Single IP, one direction active at a time (RX or TX)

Jump to

Block Diagram

CSI-2-DSI-D-PHY-Receiver-03-31-2026Expand Image

Ordering Information

The MIPI CSI/DSI IP is provided at no additional cost with the Lattice Radiant software.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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MIPI CSI/DSI IP Core - User Guide
FPGA-IPUG-02321 1.0 4/6/2026 PDF 1.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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MIPI CSI/DSI IP Core - Release Notes
FPGA-RN-02112 1.0 4/6/2026 PDF 304.7 KB

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