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  • DisplayPort IP

    IP Core

    DisplayPort IP

    Lattice has partnered with Bitec to bring the DisplayPort 1.4a compliant IP Core (with eDP 1.4 support) to the ECP5 FPGA. Supports resolutions of up to 1080p60
    DisplayPort IP
  • DisplayPort VIP Input Board

    Board

    DisplayPort VIP Input Board

    Expands the Lattice VIP board ecosystem to support DisplayPort 1.4a (DP) video input - up to 4 lanes at 1.62 or 2.7 Gbps.
    DisplayPort VIP Input Board
  • DisplayPort VIP Output Board

    Board

    DisplayPort VIP Output Board

    Expands the Lattice VIP board ecosystem to support DisplayPort 1.4a (DP) video output - up to 4 lanes at 1.62 or 2.7 Gbps.
    DisplayPort VIP Output Board
  • DisplayPort Receive Demo

    Demo

    DisplayPort Receive Demo

    Uses Bitec's DisplayPort IP core on the ECP5 FPGA in Lattice's Embedded Vision Development Kit. Compliant with DisplayPort 1.4a (including eDP 1.4 support).
    DisplayPort Receive Demo
  • DisplayPort Transmit Demo

    Demo

    DisplayPort Transmit Demo

    Uses Bitec's DisplayPort IP core on the ECP5 FPGA in Lattice's Embedded Vision Development Kit. Compliant with DisplayPort 1.4a (including eDP 1.4 support).
    DisplayPort Transmit Demo
  • MAS LIFCL Evaluation Board

    Board

    MAS LIFCL Evaluation Board

    This modular, flexible and easy-to-use CrossLink-NX 17 board is designed for video applications, including CSI2 MIPI, LVDS HDMI (through PMOD).
    MAS LIFCL Evaluation Board
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