The DisplayPort IP-core is a DisplayPort solution for FPGA implementation. It has a resource optimized footprint, and it is written in SystemVerilog. It comes with thin host driver and the application software controls the IP Core through this driver.
Compact, Easy-to-Use and Highly Versatile - This compact and easy-to-use IP-core is available as both source (DPTX) and sink (DPRX). With support for a wide range of link rates, including 1.62, 2.7, 5.4, and 8.1 Gbps, as well as eDP rates.
Easy Integration and Control - A thin host driver and API allows easy integration and control of the IP core.