DisplayPort IP Core

DisplayPort TX and RX IP for Low Power FPGAs

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The Lattice DisplayPort IP Core® is designed for transmission and reception of serial-digital video for consumer and professional displays. This IP helps users to implement a DisplayPort video interface as defined by VESA DisplayPort specifications. DisplayPort is a high-speed serial interface standard supported by industry leaders in consumer electronics HDTV, PC laptop, and PC monitors. This protocol is considered as a successor to VGA and DVI standards with support for video resolutions up to 4K video and multi-channel audio.

DisplayPort IP Core supports Lattice Nexus Series FPGAs and later versions of Lattice FPGA family.

Resource Utilization details are available in the IP Core User Guide.

Features

  • Selectable Transmit/Receive modes: Tx only, Rx only, and both Tx and Rx
  • Dynamic lane rates of 1.62, 2.70, and 5.40 Gbps
  • Dynamic one, two and four lanes support
  • Parameterized pixels per clock (PPC)- 1,2, and 4

Block Diagram

DisplayPort IP Block DiagramExpand Image

Resource Utilization

Below tables show configuration and resource utilization for LFCPNX-100-9LFG672C run on Lattice Radiant Software 2022.1 using Synplify Pro.

All the configurations listed in the resource utilization tables use these parameters: SST mode, AXI-Stream interface, 4 lanes, and 5.4 Gbps data rate per lane. There is little or no change to the resource numbers when using a data rate of 2.7 Gbps or 8.1 Gbps per lane

Utilization for DP RX
Configuration Resource Utilization
Pixels Per Clock Interface Bits Per Component Color Format Audio MST LUTs Registers EBRs
4 AXI-S 6, 8 RGB, YCbCr444, YCbCr422 No No 18244 15867 16
4 AXI-S 6, 8, 10, 12, 16 RGB, YCbCr444, YCbCr422 No No 27420 21514 25
2 AXI-S 6, 8 RGB, YCbCr444, YCbCr422 No No 17876 15459 15
2 AXI-S 6, 8, 10, 12, 16 RGB, YCbCr444, YCbCr422 No No 26795 20670 22
1 AXI-S 6, 8 RGB, YCbCr444, YCbCr422 No No 17774 15268 14
1 AXI-S 6, 8, 10, 12, 16 RGB, YCbCr444, YCbCr422 No No 26489 20263 21
4 Native 6, 8 RGB, YCbCr444, YCbCr422 No No 17803 15459 13
4 Native 6, 8, 10, 12, 16 RGB, YCbCr444, YCbCr422 No No 26658 20817 19
2 Native 6, 8 RGB, YCbCr444, YCbCr422 No No 17607 15197 13
2 Native 6, 8, 10, 12, 16 RGB, YCbCr444, YCbCr422 No No 26287 20295 19
1 Native 6, 8 RGB, YCbCr444, YCbCr422 No No 17545 15055 13
1 Native 6, 8, 10, 12, 16 RGB, YCbCr444, YCbCr422 No No 26194 19995 19
Utilization for DP TX
Configuration Resource Utilization
Pixels Per Clock Interface Bits Per Component Color Format Audio MST LUTs Registers EBRs
4 AXI-S 6, 8 RGB, YCbCr444, YCbCr422 No No 13908 11936 13
4 AXI-S 6, 8, 10, 12, 16 RGB, YCbCr444, YCbCr422 No No 13961 11990 13
2 AXI-S 6, 8 RGB, YCbCr444, YCbCr422 No No 13611 11676 12
2 AXI-S 6, 8, 10, 12, 16 RGB, YCbCr444, YCbCr422 No No 15150 12666 17
1 AXI-S 6, 8 RGB, YCbCr444, YCbCr422 No No 13333 11551 11
1 AXI-S 6, 8, 10, 12, 16 RGB, YCbCr444, YCbCr422 No No 14723 12419 16
4 Native 6, 8 RGB, YCbCr444, YCbCr422 No No 15768 13226 20
4 Native 6, 8, 10, 12, 16 RGB, YCbCr444, YCbCr422 No No 15751 13221 20
2 Native 6, 8 RGB, YCbCr444, YCbCr422 No No 13551 11752 12
2 Native 6, 8, 10, 12, 16 RGB, YCbCr444, YCbCr422 No No 15136 12720 17
1 Native 6, 8 RGB, YCbCr444, YCbCr422 No No 13401 11605 11
1 Native 6, 8, 10, 12, 16 RGB, YCbCr444, YCbCr422 No No 14751 12482 16

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
CertusPro-NX DPORT-CPNX-UT DPORT-CPNX-US

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the DisplayPort IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
DisplayPort IP Core - User Guide
FPGA-IPUG-02236 1.2 6/28/2024 PDF 4.5 MB

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