DisplayPort IP Core

DisplayPort TX and RX IP for Low Power FPGAs

The Lattice DisplayPort IP Core® is designed for transmission and reception of serial-digital video for consumer and professional displays. This IP helps users to implement a DisplayPort video interface as defined by VESA DisplayPort specifications. DisplayPort is a high-speed serial interface standard supported by industry leaders in consumer electronics HDTV, PC laptop, and PC monitors. This protocol is considered as a successor to VGA and DVI standards with support for video resolutions up to 4K video and multi-channel audio.

DisplayPort IP Core supports Lattice Nexus Series FPGAs and later versions of Lattice FPGA family.

Resource Utilization details are available in the IP Core User Guide.

Features

  • Selectable Transmit/Receive modes: Tx only, Rx only, and both Tx and Rx
  • Dynamic lane rates of 1.62, 2.70, and 5.40 Gbps
  • Dynamic one, two and four lanes support
  • Parameterized pixels per clock (PPC)- 1,2, and 4

Block Diagram

Ordering Information

Device Family Part Number
Single Seat Annual Single Seat Perpetual
CrossLink-NX DPHY-TX-CNX-US DPHY-TX-CNX-UT
Certus-NX DPHY-TX-CTNX-US DPHY-TX-CTNX-UT
Certus-N2 DPHY-TX-CN2-US DPHY-TX-CN2-UT
CertusPro-NX DPHY-TX-CPNX-US DPHY-TX-CPNX-UT
Avant-E DPHY-TX-AVE-US DPHY-TX-AVE-UT
Avant-G DPHY-TX-AVG-US DPHY-TX-AVG-UT
Avant-X DPHY-TX-AVX-US DPHY-TX-AVX-UT
MachXO5-NX DPHY-TX-XO5-US DPHY-TX-XO5-UT
Bundled MIPI-BNDL-US MIPI-BNDL-UT

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the DisplayPort IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
DisplayPort IP Core - User Guide
FPGA-IPUG-02236 1.3 6/26/2025 PDF 1010.6 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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DisplayPort IP Core - Release Notes
FPGA-RN-02071 1.0 6/27/2025 PDF 183.9 KB

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