DisplayPort IP Core

DisplayPort TX and RX IP for Low Power FPGAs

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The Latticetm DisplayPorttm IP core is designed for transmission and reception of serial-digital video for consumer and professional displays. This IP helps you to implement a DisplayPort video interface as defined by the Video Electronics Standards Association (VESA) DisplayPort specifications. DisplayPort is a high-speed serial interface standard supported by industry leaders in consumer electronics high-definition television (HDTV), personal computer (PC) laptop, and PC monitors.

Resource Utilization details are available in the IP Core User Guide

Features

  • Selectable transmit/receive modes: Tx only, Rx only, and both Tx and Rx
  • Static pixels per clock (PPC): 4
  • Dynamic lane rates of 1.62, 2.7, 5.4, and 8.1 Gbps
  • Dynamic 1, 2, and 4 lanes support
  • Dynamic bits per color component (BPC): 6, 8, 10, 12, and 16

Block Diagram

DisplayPortExpand Image

Ordering Information

Device Family Part Number
Single Seat Annual Single Seat Perpetual
CertusPro-NX DPORT-CPNX-US DPORT-CPNX-UT

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the DisplayPort IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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DisplayPort Driver API Reference
FPGA-TN-02423 1.0 12/11/2025 PDF 619 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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DisplayPort IP Core - User Guide
FPGA-IPUG-02236 1.4 12/11/2025 PDF 2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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DisplayPort IP Core - Release Notes
FPGA-RN-02071 1.1 12/11/2025 PDF 228.5 KB

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