DisplayPort IP Core

DisplayPort TX and RX IP for Low Power FPGAs

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The Lattice DisplayPort IP Core is designed for transmission and reception of serial-digital video for consumer and professional displays. This IP helps users implement DisplayPort video interface as defined by VESA DisplayPort specifications. DisplayPort is a high-speed serial interface standard supported by industry leaders in Consumer electronics, Industrial and Automotive. This protocol is considered a successor to VGA and DVI standards with support for video resolutions up to 8Kx4K video and adds audio.

DisplayPort IP Core supports Lattice Nexus Series FPGAs and later versions of Lattice FPGA family.

Dynamic and Parameterized Lanes Support – Implements a receiver and transmitter per lane with 1, 2 and 4 lanes (parameterized for RX and dynamic for TX) at 1.62, 2.7, 5.4 and 8.1 Gbps.

AXI4-Lite and AXI4-Stream Support – This IP supports commonly used standard interfaces for configuration and video data such as AXI4-Lite and AXI4-Stream respectively. It helps user to easily plug-in IP in existing/upcoming system.

Features

  • SST Video Stream Mode
  • Supports up to 2 channel audio (LPCM audio)
  • Supports AUX channel, up to 16 bytes messaging per transaction
  • Dynamic Pixel Format Support (RGB888, YCbCr444 and YCbCr422)
  • Choice of native video interface or AXI-Stream for video input/output

Block Diagram

DisplayPort IP Block DiagramExpand Image

Resource Utilization

Below tables show configuration and resource utilization for LFCPNX-100-9LFG672C run on Lattice Radiant Software 2022.1 using Synplify Pro.

All the configurations listed in the resource utilization tables use these parameters: SST mode, AXI-Stream interface, 4 lanes, and 5.4 Gbps data rate per lane. There is little or no change to the resource numbers when using a data rate of 2.7 Gbps or 8.1 Gbps per lane

Utilization for DP RX without Audio
Configuration Resource Utilization
Pixels Per Clock Bits Per Component Color Format Registers LUTs EBRs
4 8 RGB 14757 17444 55
4 16 RGB 15939 18186 55
2 8 RGB 14257 16990 28
2 16 RGB 15439 17009 28
1 8 RGB 14010 16730 27
1 16 RGB 15200 16790 27
4 8 YCbCr444 14757 17443 55
4 16 YCbCr444 15939 18283 54
2 8 YCbCr444 14257 16955 28
2 16 YCbCr444 15439 17796 28
1 8 YCbCr444 15439 17009 28
1 16 YCbCr444 15192 17551 27
4 8 YCbCr422 16921 19318 55
4 16 YCbCr422 17410 21413 55
2 8 YCbCr422 16497 18906 28
2 16 YCbCr422 16986 21054 28
1 8 YCbCr422 16302 18789 27
1 16 YCbCr422 16821 20817 27
Utilization for DP RX with Audio
Configuration Resource Utilization
Pixels Per Clock Bits Per Component Color Format Registers LUTs EBRs
4 8 RGB 19529 22646 67
4 16 RGB 20706 23333 67
2 8 RGB 19025 22199 40
2 16 RGB 20208 22948 40
1 8 RGB 18776 21977 39
1 16 RGB 19744 22830 39
4 8 YCbCr444 19526 22596 67
4 16 YCbCr444 20634 23311 67
2 8 YCbCr444 19025 22174 40
2 16 YCbCr444 19987 22820 40
1 8 YCbCr444 18779 22001 39
1 16 YCbCr444 19743 22765 39
4 8 YCbCr422 21608 24473 67
4 16 YCbCr422 21959 26308 67
2 8 YCbCr422 21268 24138 40
2 16 YCbCr422 21775 26162 40
1 8 YCbCr422 20987 24030 39
1 16 YCbCr422 21575 25930 39
Utilization for DP TX without Audio
Configuration Resource Utilization
Pixels Per Clock Bits Per Component Color Format Registers LUTs EBRs
4 8 RGB 17339 16290 26
4 16 RGB 17855 16592 26
2 8 RGB 17127 16008 23
2 16 RGB 17680 16156 23
1 8 RGB 17099 15966 22
1 16 RGB 17618 16021 22
4 8 YCbCr444 17339 16290 26
4 16 YCbCr444 17855 16592 26
2 8 YCbCr444 17127 16008 23
2 16 YCbCr444 17680 16156 23
1 8 YCbCr444 17099 15966 22
1 16 YCbCr444 17618 16021 22
4 8 YCbCr422 17208 15866 26
4 16 YCbCr422 17231 16008 26
2 8 YCbCr422 17000 15846 23
2 16 YCbCr422 17033 15561 23
1 8 YCbCr422 16933 15771 22
1 16 YCbCr422 16991 15655 22
Utilization for DP TX with Audio
Configuration Resource Utilization
Pixels Per Clock Bits Per Component Color Format Registers LUTs EBRs
4 6 RGB 17894 18460 41
4 8 RGB 18084 17679 44
4 16 RGB 18631 18443 44
2 6 RGB 17737 18265 38
2 8 RGB 17915 17890 41
2 16 RGB 18439 18303 41
1 6 RGB 17699 18140 37
1 8 RGB 17870 17782 40
1 16 RGB 18388 17969 40
4 8 YCbCr444 18084 17679 44
4 16 YCbCr444 18631 18443 44
2 8 YCbCr444 17915 17890 41
2 16 YCbCr444 18439 18303 41
1 8 YCbCr444 17870 17782 40
1 16 YCbCr444 18388 17969 40
4 8 YCbCr422 17974 17714 44
4 16 YCbCr422 17999 18020 44
2 8 YCbCr422 17764 17761 41
2 16 YCbCr422 17824 17714 41
1 8 YCbCr422 17727 17608 40
1 16 YCbCr422 17762 17539 40

Ordering Information

  Part Number
Device Family Single Machine Annual Site Perpetual
CertusPro-NX DPORT-CPNX-US DPORT-CPNX-UT

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the DisplayPort IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
DisplayPort IP Core - User Guide
FPGA-IPUG-02236 1.0 7/20/2023 PDF 3.1 MB

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