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  • Scene Segmentation Reference Design

    Reference Design

    Scene Segmentation Reference Design

    Efficient and low power approach for implementing scene segmentation using Lattice CrossLink-NX FPGA
    Scene Segmentation Reference Design
  • PCIe Basic Demo on Crosslink-NX PCIe Bridge Board

    Demo

    PCIe Basic Demo on Crosslink-NX PCIe Bridge Board

    The PCIe Basic Demo allows you to control three 7 segment LEDs and manipulate the onboard memory of the FPGA through the PCIe slot.
    PCIe Basic Demo on Crosslink-NX PCIe Bridge Board
  • PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    Demo that displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.
    PCIe Colorbar Demo for Lattice Nexus-based FPGAs
  • PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.
    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs
  • PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demonstrates the multifunction capabilities of the Crosslink-NX FPGA that allows access to GPIO, MDIO and I2C registers.
    PCIe Multifunction Demo for Lattice Nexus-based FPGAs
  • User Tracking and Onlooker Detection Demonstration

    Demo

    User Tracking and Onlooker Detection Demonstration

    Sample demonstration for detection and tracking of multiple human faces running on a low power general purpose FPGA using CNN Model
    User Tracking and Onlooker Detection Demonstration
  • CrossLink-NX Voice and Vision Machine Learning Board

    Board

    CrossLink-NX Voice and Vision Machine Learning Board

    Designed for low-power machine learning applications with Lattice sensAI and CrossLink-NX. Includes image sensors, microphones, HyperRAM, and expansion ports.
    CrossLink-NX Voice and Vision Machine Learning Board
  • CrossLink-NX-33 Voice and Vision Machine Learning Board

    Board

    CrossLink-NX-33 Voice and Vision Machine Learning Board

    Designed for low-power machine learning applications with Lattice sensAI and CrossLink-NX-33. Includes expansion ports and audio-based AI applications tools.
    CrossLink-NX-33 Voice and Vision Machine Learning Board
  • Timer/Counter IP Core

    IP Core

    Timer/Counter IP Core

    Timer/Counter IP used to track timeouts in the system. Target devices are Certus-NX and Crosslink-NX.
    Timer/Counter IP Core
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    Propel IP Module: 32-bit RISC-V processor core with optional Timer and PIC sub-modules, connects via AHB-Lite bus to other Propel IP modules and more.
    RISC-V MC CPU IP Core
  • CrossLink-NX Evaluation Board

    Board

    CrossLink-NX Evaluation Board

    For general evaluation and development with CrossLink-NX, includes many flexible interfaces such as FMC and PMOD with generous device IO access
    CrossLink-NX Evaluation Board
  • PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    IP Core

    PCI Express x1 & x4 IP Core for Nexus-based FPGAs

    The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express x1 & x4 IP Core for Nexus-based FPGAs
  • User Background Blurring Demonstration

    Demo

    User Background Blurring Demonstration

    Efficient and low power approach for implementing user background blurring using Lattice CrossLink-NX FPGA
    User Background Blurring Demonstration
  • Human Face Identification Reference Design

    Reference Design

    Human Face Identification Reference Design

    Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
    Human Face Identification Reference Design
  • Object Counting AI

    Reference Design

    Object Counting AI

    An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
    Object Counting AI
  • CNN Plus Accelerator IP

    IP Core

    CNN Plus Accelerator IP

    Implement Ultra-Low Power AI solutions with CNNs. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    CNN Plus Accelerator IP
  • Helion IONOS Image Signal Processing IP Portfolio

    IP Core

    Helion IONOS Image Signal Processing IP Portfolio

    Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.
    Helion IONOS Image Signal Processing IP Portfolio
  • CSI-2/DSI D-PHY Receiver

    IP Core

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