​​I/O Aggregation Over USB with CrossLinkU-NX Reference Design​

Accelerating USB 2.0/3.2 (5 Gbps) Interface Innovation

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​​The I/O Aggregation Over USB with CrossLinkU-NX Reference Design create plug-and-play peripheral expansion on USB-enabled FPGA and signal protocol conversion from USB to I2C, SPI, and GPIO. The Lattice Semiconductor I/O Aggregation Over USB2 reference design provides developers a template to bridge USB to several interfaces defined below from a Windows PC and provides this conversion for Lattice Semiconductor CrossLinkU-NX devices.​

Features

  • Wrapper RTL includes RISC-V, System Memory, and AHB bridge for USB enumeration
  • Maximum 8 endpoints can be flexibly configured as user selected peripheral:
    • GPIO Input
    • GPIO Output
    • I2C Controller
    • SPI Controller
  • Windows drivers and Python script to communicate to the peripherals

Block Diagram

​I-O Aggregation Over USB Block DiagramExpand Image

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
I/O Aggregation Over USB with CrossLinkU-NX Reference Design – Source Code​
12/20/2024 ZIP 73.8 MB
I/O Aggregation Over USB with CrossLinkU-NX Reference Design – User Guide​
FPGA-RD-02288 2.0 12/20/2024 PDF 3.6 MB

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