Tightly-Coupled Memory (TCM) IP Core

Low-Latency Automatic Selection of the Best Memory Type

This document provides technical information about the Tightly-Coupled Memory (TCM) IP and aims to provide information essential for IP/system developing, verification, integration, testing, and validation.

The design is implemented in Verilog HDL. It can be configured and generated using the Lattice Propel™ Builder software, and implemented using the Lattice Diamond and Lattice Radiant Software. It supports Lattice Avant™, MachXO5™-NX, Certus™-NX, CertusPro™-NX, and CrossLink™-NX FPGA devices.

Resource Utilization details are available in the IP Core User Guide.

Features

  • Configurable as single-port or dual-port memory
  • Core memory can be implemented as EBR , LRAM or Distributed RAM
  • Supports ROM and RAM mode
  • Supports byte enable configurable
  • Supports byte writes when used with compatible hardware

Block Diagram

Ordering Information

The Tightly-Coupled Memory IP Core is provided at no additional cost with Lattice Propel Builder.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
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Tightly-Coupled Memory IP Core – Lattice Propel Builder 2024.1 User Guide
FPGA-IPUG-02255 1.0 6/28/2024 PDF 877.3 KB

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