Tightly-Coupled Memory (TCM) IP Core

Low-Latency Automatic Selection of the Best Memory Type

The TCM Memory Module uses Embedded Block RAMs (EBR) or Distributed Memory in the Lattice Avant family devices. As for CrossLink-NX and Certus-NX, CertusPro-NX, and MachXO5-NX family devices, Large RAMs are also used. The memory implementation can be configured as true dual-port, single-port, or read-only memory. The number of ports and read/write configuration of the TCM IP Module automatically select the best type of memory for the user-selected application.

The design is implemented in Verilog HDL. It can be configured and generated using the Lattice Propel™ Builder software, and implemented using the Lattice Diamond and Lattice Radiant Software. It supports Lattice Avant™, MachXO5™-NX, Certus™-NX, CertusPro™-NX, and CrossLink™-NX FPGA devices.

Local Bus Interface - The TCM Memory Module is designed to be fully compatible with the local bus interface. It can be configured as single-port or dual-port interfaces, depending on if single-port or dual-port memory is needed along with RAM or ROM configuration.

FIFO Interface - There is a dedicated FIFO interface shared with the port S1. This interface is used to inject FIFO data from a FIFO stream, typically used to upload firmware values to the core memory.

Unaligned Access Feature - The Large RAM Module supports RISC-V compressed instruction chunks of data and shifts them. If RISC-V needs to read the upper 16 bit of data in some address, this feature enables adding support for shifting the upper 16 bits of output into the lower 16 bits, padding the upper bits with 0.


  • Configurable as single-port or dual-port memory
  • Core memory can be implemented as EBR , LRAM or Distributed RAM
  • Supports ROM and RAM mode
  • Supports byte enable configurable
  • Supports byte writes when used with compatible hardware

Block Diagram


Quick Reference
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Tightly-Coupled Memory - Lattice Propel 2023.1
FPGA-IPUG-02231 1.1 8/16/2023 PDF 821.5 KB

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