Tightly-Coupled Memory (TCM) IP Core

Low-Latency Automatic Selection of the Best Memory Type

The Tightly-Coupled Memory (TCM) IP ensures low-latency automatic selection of the best memory type for user-selected application. The design is implemented in Verilog HDL.

Resource Utilization details are available in the IP Core User Guide.

Features

  • Configurable as single-port or dual-port memory
  • Core memory can be implemented as EBR , LRAM or Distributed RAM
  • Supports ROM and RAM mode
  • Supports byte enable configurable
  • Supports byte writes when used with compatible hardware

Block Diagram

Ordering Information

The Tightly-Coupled Memory IP Core is provided at no additional cost with Lattice Propel Builder.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
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Tightly-Coupled Memory IP Module User Guide - Lattice Propel Builder
FPGA-IPUG-02281 1.0 6/26/2025 PDF 820.5 KB

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