The Tightly-Coupled Memory (TCM) IP ensures low-latency automatic selection of the best memory type for user-selected application. The design is implemented in Verilog HDL.
Resource Utilization details are available in the IP Core User Guide.
The Tightly-Coupled Memory IP Core is provided at no additional cost with Lattice Propel Builder.
*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.