Tightly-Coupled Memory (TCM) IP Core

Low-Latency Automatic Selection of the Best Memory Type

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The Tightly-Coupled Memory (TCM) IP ensures low-latency automatic selection of the best memory type for user-selected application. The design is implemented in Verilog HDL.

Resource Utilization details are available in the IP Core User Guide.

Features

  • Configurable as single-port or dual-port memory
  • The Core memory can be implemented as EBR , LRAM or Distributed RAM
  • Supports the ROM and the RAM mode
  • Supports configurable byte enables
  • Supports byte writes when used with compatible hardware

Block Diagram

Tightly-Coupled Memory (TCM) IP Core Block Diagram放大图片

Ordering Information

The Tightly-Coupled Memory IP Core is provided at no additional cost with Lattice Propel Builder.

Documentation

快速参考
标题 编号 版本 日期 格式 文件大小
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Tightly-Coupled Memory IP Core – Lattice Propel Builder 2025.1.1 User Guide
FPGA-IPUG-02299 1.0 10/10/2025 PDF 971.5 KB

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