Smart Consumer Robots and Toys

Powerful, Low Power FPGAs Enable Next Generation Robots and Toys

Next generation of consumer robots and toys are embedding a range of sensors to drive rich user experiences and human-like interfacing. Designers are taking advantage of flexibility in sensors choices, powerful low power edge processors, and ability to aggregate data from multiple sensors to drive these devices.

Lattice’s smart solutions running on optimized low power FPGAs provide:

  • Low power on-device AI for object detection, identification, counting, and human-machine interfacing
  • ISP and other processing to collect quality image, sound, and data from sensors
  • Flexible and low latency sensor data aggregation, bridging, and buffering from a wide variety of sensors
  • Accurate, low power, and predictable motor control to drive devices’ movement

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Block Diagram

Robots and Toys

Example Use Cases

Low Power AI Processing

  • Low Power on-device NN based processing
  • Reduced data traffic to the cloud, improving security and privacy and reducing bandwidth usage
  • Object detection, classification, counting and HMI including gestures and voice based commands

Motor Control

  • Low latency programmable motor control
  • Ability to interface with a wide variety of motors
  • Predictable performance to meet safety requirements

Audio Bridging

  • Connect up to 8 microphones to a processor
  • Audio data buffering to offload the processor
  • Support I2S, PDM microphone interfacing
  • Up to 1 Mb of on device RAM for buffering

Image Sensor Bridging

  • Connect a wide variety of image sensors to processors
  • MIPI PHYs supports up to 2.5 Gbps/lane, up to four lanes
  • Flexible host interfacing including CSI, SPI, PCIe
  • Flexible processing for video data muxing and stitching

Sensor Fusion and I/O Expansion

  • Interface to wide variety of sensors to create rich user experience
  • Flexible preprocessing including arbitration, time stamping, and filtering
  • Create programmable sensor fusion algorithms

Low Latency Sensor Bridging

  • Take advantage of parallel FPGA architecture to simultaneously collect data from multiple sensors
  • Interface to wide variety of sensors to create rich user experience
  • Flexible preprocessing including arbitration, time stamping, and filtering

Reference Designs

Human Face Identification Reference Design

Reference Design

Human Face Identification Reference Design

Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
Human Face Identification Reference Design
人感検出

Reference Design

人感検出

Uses Lattice sensAI IP to continuously search for the presence of a human and reports results. Can be adapted to detect any other object.
人感検出
CertusPro-NX N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

Reference Design

CertusPro-NX N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

Modular MIPI/D-PHY Reference Design - Multiple channel image data concatenated horizontally line by line and offers up to eight-channel aggregation.
CertusPro-NX N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation
SLVS-EC to MIPI CSI-2 Reference Design

Reference Design

SLVS-EC to MIPI CSI-2 Reference Design

Modular MIPI/D-PHY Reference Design - Support advance camera and display interconnections in mobile devices that enable higher performance sensor with optimized power.
SLVS-EC to MIPI CSI-2 Reference Design

Demos

CSI-2 PCIe Bridge Demonstration

Demo

CSI-2 PCIe Bridge Demonstration

This design demonstrates the functionality of transferring MIPI CSI-2 camera video data to computer via PCIe with a Direct Memory Access (DMA) engine.
CSI-2 PCIe Bridge Demonstration
Generic Soft SPI Master Controller Demonstration

Demo

Generic Soft SPI Master Controller Demonstration

This demo implements the Generic Soft SPI Master Controller Reference Design by performing simple transactions to the external SPI Flash device found in the MachXO3-9400 Development Board
Generic Soft SPI Master Controller Demonstration

IP Cores

CNN Plus Accelerator IP Core

IP Core

CNN Plus Accelerator IP Core

CNN Plus IP is a flexible accelerator IP that simplifies implementation of Ultra-Low power AI by leveraging capabilities of Lattice FPGAs.
CNN Plus Accelerator IP Core
CSI-2 / DSI D-PHY レシーバ

IP Core

CSI-2 / DSI D-PHY レシーバ

MIPI D-PHY はカメラやディスプレイの標準的なインタフェースです。この IP を使用すると FPGA に D-PHY レシーバを実装できます。
CSI-2 / DSI D-PHY レシーバ

Development Kits & Boards

CertusPro-NX Versa Board

Board

CertusPro-NX Versa Board

CertusPro-NX Versa Board supports a wide range industry standards such as MIPI, SFP+, 10 GbE, LPDDR4 and PCIe (Gen3) for rapid prototyping and testing.
CertusPro-NX Versa Board
CrossLink-NX 評価ボード

Board

CrossLink-NX 評価ボード

CrossLink-NX 評価ボードは 40K ロジックセルのCrossLink-NXを搭載: ほとんどの I/O に簡単にアクセス可能、FPGA の PCIe 5G SERDES: FPGA メザニンカード (FMC)、Raspberry Pi、MIPI CSI-2、D-PHY、拡張用汎用ヘッダ
CrossLink-NX 評価ボード
CrossLinkPlus LIF-MDF6000 Master Link Board

Board

CrossLinkPlus LIF-MDF6000 Master Link Board

This kit with the LIF-MDF6000 Master Link Revision B Board can be used to build bridging solutions between various video formats. You can use this hardware to validate your own designs.
CrossLinkPlus LIF-MDF6000 Master Link Board

Support

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