Byte to Pixel Converter IP Core

Convert Parallel Data From a D-PHY Receiver into Pixel Format

Due to the higher demand for better displays, bridging applications has become increasingly popular. One very common application interface is the Mobile Industry Processor Interface (MIPI®) D-PHY. It was developed primarily to support camera and display interconnections in mobile devices, and it has become the industry’s primary high-speed PHY solution for these applications in smartphones today. It is typically used in conjunction with MIPI Camera Serial Interface-2 (CSI-2) and MIPI Display Interface (DSI) protocol specifications. MIPI D-PHY meets the demanding requirements of low-power, low noise generation, and high noise immunity that mobile phone designs demand.

Lattice Semiconductor Byte-to-Pixel Converter IP converts CSI-2/DSI standard based video payload packets from D-PHY Receiver Module output to pixel format. In addition, Byte-to-Pixel Converter IP generates camera/video control signals in the pixel domain, based on CSI-2 or DSI synchronization packets.


  • MIPI DSI compatible video formats
  • MIPI CSI-2 compatible video formats
  • 1-, 2-, or 4-lane inputs
  • 8-bit (gear 8) or 16-bit (gear 16) inputs per lane
  • 1, 2, or 4 output pixels per pixel clock cycle

Block Diagram

Byte to Pixel Converter

Resource Utilization

IP Configuration for Nexus Family
Device LUTs Registers sysMem EBRs Programmable I/O
CSI2,RAW10,Byte Side Clock
Frequency 100 MHz, Pixel Side
Clock Frequency 80 MHz, Word Count 720
369 287 1 51
CSI2,RGB888,Byte Side Clock
Frequency 150 MHz, Pixel Side
Clock Frequency 100 MHz, Word Count 720
399 324 1 73
CSI2,RGB888, Number of RX
Lanes 4, Byte Side Clock
Frequency 50 MHz, Pixel Side
Clock Frequency 160 MHz, Word Count 2050
495 363 2 75
CSI2,RGB888, Number of RX
Lanes 4, Byte Side Clock
Frequency 112.5 MHz, Pixel Side
Clock Frequency 150 MHz, Word Count 3600
421 386 2 89
DSI,RGB666, Number of RX
Lanes 1, Byte Side Clock
Frequency 108 MHz, Pixel Side
Clock Frequency 96 MHz, Word Count 2160
534 337 1 68
DSI,RGB666, Number of RX
Lanes 2, Byte Side Clock
Frequency 140.625 MHz, Pixel
Side Clock Frequency 125 MHz,
Number of Output Pixels 2,
Word Count 21600
649 427 1 102

Note: The distributed RAM utilization is accounted for in the total LUT4 utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

IP Configuration for CrossLink Family
IP User-Configurable Parameters Slices LUTs Registers sysMem EBRs Programmable I/O
Gear 16,
2 pixel output
463 511 548 6 0
Gear 8,
2 pixel output
267 289 333 3 0
Gear 16,
1 pixel output
249 259 305 3 0
Gear 8,
1 pixel output
215 238 264 2 0

Ordering Information

The Byte to Pixel core is available for FREE for use in Diamond design software.

For Radiant design software, the Byte to Pixel core must be purchased:

  Part Number
Device Family Single Design Multi-Site Subscription

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the Byte-to-Pixel IP core, please contact your local Lattice Sales Office.


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