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  • Hand Gesture Detection

    Reference Design

    Hand Gesture Detection

    Implements a low power AI based system to detect hand gestures using an IR image sensor
    Hand Gesture Detection
  • Key Phrase Detection

    Demo

    Key Phrase Detection

    Uses artificial intelligence (AI) to detect a specific key-phrase using a tiny, low-power iCE40 UltraPlus FPGA
    Key Phrase Detection
  • Single Wire Signal Aggregation Demonstration

    Demo

    Single Wire Signal Aggregation Demonstration

    Single Wire Signal Aggregation Demonstration contains two boards to demonstrate the complete working design in a stand-alone configuration.
    Single Wire Signal Aggregation Demonstration
  • Single Wire Signal Aggregation Reference Design

    Reference Design

    Single Wire Signal Aggregation Reference Design

    Single Wire Signal Aggregation Reference Design is configurable, the number of I2C/I2S busses and GPIOs and single wire protocol packet length can be adjusted.
    Single Wire Signal Aggregation Reference Design
  • Key Phrase Detection

    Reference Design

    Key Phrase Detection

    Continuous searches for a key phrase utterance via a digital MEMS microphone. Can be re-configured to work with any trained word or phrase.
    Key Phrase Detection
  • Human Presence Detection

    Reference Design

    Human Presence Detection

    Uses Lattice sensAI IP to continuously search for the presence of a human and reports results. Can be adapted to detect any other object.
    Human Presence Detection
  • Convolutional Neural Network (CNN) Compact Accelerator

    IP Core

    Convolutional Neural Network (CNN) Compact Accelerator

    Implement AI solutions with CNNs or BNNs that have power consumption in the mW range. Works with Lattice Neural Network Compiler software tool.
    Convolutional Neural Network (CNN) Compact Accelerator
  • I3C Controller IP Core

    IP Core

    I3C Controller IP Core

    I3C Controller IP Core is a two-wire, bi-directional serial bus designed for use with many sensor secondary devices controlled by a single I3C controller.
    I3C Controller IP Core
  • I3C Target IP Core

    IP Core

    I3C Target IP Core

    I3C Target IP Core enables greater than 10-fold speed improvements, more effective bus power management, and backward compatibility with I2C devices.
    I3C Target IP Core
  • Hand Gesture Detection

    Demo

    Hand Gesture Detection

    Uses artificial intelligence (AI) to implement hand gesture detection algorithm using a tiny, low-power iCE40 UltraPlus FPGA
    Hand Gesture Detection
  • HM01B0 UPduino Shield

    Board

    HM01B0 UPduino Shield

    A complete development kit for implementing Artificial Intelligence (AI) using vision and sound as sensory inputs to a low-cost, low-power iCE40 UltraPlus FPGA.
    HM01B0 UPduino Shield
  • Human Face Detection AI Demo

    Demo

    Human Face Detection AI Demo

    Uses Lattice sensAI IP to detect human faces on a tiny, low-power iCE40 UltraPlus FPGA implementing AI at the edge. Adaptable to detect other objects.
    Human Face Detection AI Demo
  • Human Presence Detection AI Demo

    Demo

    Human Presence Detection AI Demo

    Uses an artificial intelligence (AI) algorithm to detect human presence with either the powerful ECP5 FPGA, or small, low-power iCE40 UltraPlus FPGA.
    Human Presence Detection AI Demo
  • USB 2.0 Device with FIFO Interface (USB20HF)

    IP Core

    USB 2.0 Device with FIFO Interface (USB20HF)

    USB20HF IP Core provides FIFO & ULPI interface. It supports High Speed and Full Speed functionality for 15 IN/OUT endpoints.
    USB 2.0 Device with FIFO Interface (USB20HF)
  • DPControl iCEVision Board

    Board

    DPControl iCEVision Board

    A highly flexible and expandable prototyping platform for vision based AI and many other applictions
    DPControl iCEVision Board
  • iCE40 UltraPlus Breakout Board

    Board

    iCE40 UltraPlus Breakout Board

    General purpose board for evaluation and development with iCE40 UltraPlus. Includes access to all IO, high-current LED, switches, etc.
    iCE40 UltraPlus Breakout Board
  • Single Wire Signal Aggregation Development Board

    Board

    Single Wire Signal Aggregation Development Board

    Single Wire Signal Aggregation Dev Board uses the smallest form factor FPGAs to perform as a Single-Wire aggregator for I2C, I2S, UART, & GPIO signaling.
  • 8N1 UART Transceiver Reference Design

    Reference Design

    8N1 UART Transceiver Reference Design

    8-bit data, no parity, and 1 stop bit Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel and parallel to serial conversions on data characters received from a peripheral device or CPU
    8N1 UART Transceiver Reference Design
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