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  • RISC-V Nano CPU IP Core

    IP Core

    RISC-V Nano CPU IP Core

    The RISC-V Nano CPU IP contains a 32-bit RISC-V processor core that supports the RV32I instruction set and a lightweight interrupt merge controller.
    Certus-N2, Avant-E, Avant-G, Avant-X, MachXO5-NX, CrossLink-NX, CertusPro-NX, Certus-NX, MachXO3D, MachXO2, iCE40 UltraPlus, MachXO4 
    Soft Processor, RISC-V, Lattice Propel, Lattice Diamond, Lattice Radiant, Defense, AHB-Lite 
    RISC-V Nano CPU IP Core
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory (TCM) IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Certus-N2, Avant-E, Avant-G, Avant-X, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX 
    Embedded Ram, FIFO, Lattice Propel, Lattice Diamond, Lattice Radiant, Defense 
    Tightly-Coupled Memory (TCM) IP Core
  • RISC-V AXI4 I/O Physical Memory Protection (IOPMP) IP Core

    IP Core

    RISC-V AXI4 I/O Physical Memory Protection (IOPMP) IP Core

    RISC-V I/O Memory Protection IP protects the data in specific memory regions and allows the CPU to control external AXI manager access to AXI subordinates at run-time.
    Avant-E, Avant-G, Avant-X, MachXO5-NX, CrossLink-NX, Certus-NX, CertusPro-NX, Lattice Propel System Design Environment 
    Soft Processor, RISC-V, Lattice Propel, Lattice Diamond, Lattice Radiant, Defense 
    RISC-V AXI4 I/O Physical Memory Protection (IOPMP) IP Core
  • PIC IP Core

    IP Core

    PIC IP Core

    Lattice Semiconductor PIC soft IP with configurable 1~8 interrupt inputs and 32-bit AHB-L interface for Mach-NX FPGA
    Mach-NX, MachXO5-NX 
    AHB-Lite, Lattice Propel, Lattice Diamond, Lattice Sentry, Lattice Sentry PFR IP Package, Security 
    PIC IP Core
  • Timer/Counter IP Core

    IP Core

    Timer/Counter IP Core

    The Lattice Semiconductor Timer/Counter IP is used to track timeouts in the system, and it generates an interrupt to the CPU when a timeout is detected.
    Certus-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X, CertusPro-NX, CrossLink, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 LP/HX, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP2/M, LatticeECP3, LatticeSC/M, LatticeXP2, Mach-NX, MachXO, MachXO2, MachXO3, MachXO3D, MachXO5-NX, Certus-N2 
    AMBA, Lattice Propel, Lattice Diamond, Lattice Radiant, APB, AHB-Lite, Lattice Sentry, Lattice Sentry PFR IP Package, Security 
    Timer/Counter IP Core
  • Lattice Sentry I2C Filter IP Core

    IP Core

    Lattice Sentry I2C Filter IP Core

    Sentry I2C Filter IP Core provides an interface between I2C bus devices and a host processor while protecting against common I2C bus vulnerabilities.
    Mach-NX, MachXO3D, MachXO5-NX, MachXO4 
    I2C, AHB-Lite, AHB-L, Lattice Propel, Lattice Sentry, Security, AMBA, FPGA, SMBus, RoT, Lattice Diamond, Lattice Sentry PFR IP Package, Defense 
    Lattice Sentry I2C Filter IP Core
  • DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core

    IP Core

    DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core

    LTPI IP Core is an Open Computer Project Data Center – Secure Control Module Standards compatible solution which is introduced in the DC-SCM 2.0 Specification.
    CertusPro-NX, CrossLink-NX, Certus-NX, MachXO3, MachXO3D, MachXO5-NX, Mach-NX, MachXO4 
    CRC, LVDS, LTPI, AMBA, APB, Lattice Diamond, Lattice Radiant, Lattice Sentry, OCP 
    DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core
  • LVDS Tunneling Protocol and Interface Reference Design

    Reference Design

    LVDS Tunneling Protocol and Interface Reference Design

    The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.
    MachXO5-NX, MachXO3D, MachXO3, Mach-NX 
    CRC, LVDS, I2C, GPIO, UART, LTPI, AMBA, APB, Lattice Diamond, Lattice Propel, OCP 
    LVDS Tunneling Protocol and Interface Reference Design
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