DC-SCM LVDS Tunneling Protocol and Interface IP Core

Compliant with OCP DC-SCM 2.0 and Aggregate Multiple Data Channel

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The Lattice Semiconductor DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core is an Open Computer Project (OCP) Data Center – Secure Control Module (DC-SCM) Standards compatible solution which is introduced in the DC-SCM 2.0 Specification. LTPI is a protocol and interface designed for tunneling various low-speed signals between Host Processor Module (HPM) and Secure Control Module (SCM).

Resource Utilization details are available in the IP Core User Guide.

Features

  • Compliant with OCP DC-SCM 2.0 LTPI Rev1.1 Specifications version 1.1 (May 2024).
  • Link initialization, discovery, and negotiation.
  • Supports Multi-Channel Serial Interface.
  • Supports LVDS and subLVDS.
  • Supports up to five channels aggregation/disaggregation in total.

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Block Diagram

DC-SCM LVDS Tunneling Protocol and Interface IP Core Block DiagramExpand Image

Performance and Size

MachXO3
Configuration Registers Slice LUTs EBRs
LCMXO3L-9400C-6BG484C
IP Mode = SCM
DDR == Enabled
Low Latency I/O == 16
Normal Latency I/O == 16
I2C == 1 (Controller)
UART == 2
OEM == 16
Data Channel == Enabled		 2212 1193 2356 6
LCMXO3L-9400C-6BG484C
IP Mode = HPM
DDR == Enabled
Low Latency I/O == 16
Normal Latency I/O == 16
I2C == 1 (Target)
UART == 2
OEM == 16
Data Channel == Enabled		 2168 1233 2417 6

1. Utilization data is generated using a sample IP configuration for LCMXO3L-9400C-6BG484C with Strategy set to default setting. Number may vary when using a different software version or targeting a different device density, synthesis tool, or speed grade. For Static Timing Analysis, IP is tested in both -5 and -6 speed grade. For better performance in certain cases, user is recommended to run multiple iterations of Place and Route and/or set Optimization Goal to Timing in Strategy Section of SW tool.

MachXO5-NX
Configuration Registers Slice LUTs EBRs
LFMXO5-25-9BBG400C
IP Mode = SCM
DDR == Enabled
Low Latency IO == 16
Normal Latency IO == 16
I2C == 1 (Controller)
UART == 2
OEM == 16
Data Channel == Enabled		 2028 1806 2258 3
LFMXO5-25-9BBG400C
IP Mode = HPM
DDR == Enabled
Low Latency IO == 16
Normal Latency IO == 16
I2C == 1 (Target)
UART == 2
OEM == 16
Data Channel == Enabled		 1985 1762 2259 3

1. Utilization data is generated using a sample IP configuration for LFMXO5-25-9BBG400C with Strategy set to default setting. Number may vary when using a different software version or targeting a different device density, synthesis tool, or speed grade. For better performance in certain cases, user is recommended to run multiple iterations of Place and Route and/or set Optimization Goal to Timing in Strategy Section of SW tool.

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
MachXO5-NX LTPI-XO5-UT -
MachXO3D LTPI-XO3D-UT -
MachXO3 LTPI-XO3-UT -
Mach-NX LTPI-MNX-UT -

Evaluate: To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

Purchase: To find out how to purchase the IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
DC-SCM LTPI IP User Guide
FPGA-IPUG-02200 1.9 12/20/2024 PDF 2.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
DC-SCM LTPI IP Release Notes
FPGA-RN-02021 1.0 12/20/2024 PDF 207.4 KB

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