DC-SCM LVDS Tunneling Protocol and Interface IP Core

Compliant with OCP DC-SCM 2.0 and Aggregate Multiple Data Channel

The Lattice Semiconductor DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core is an Open Computer Project (OCP) Data Center – Secure Control Module (DC-SCM) Standards compatible solution which is introduced in the DC-SCM 2.0 Specification. DC‑SCM aims to move common server management, security and control features from a typical motherboard into a module designed in different form factors (horizontal, vertical). The basic idea is to enable a common security and management module form and interface which can be used across datacenter platforms.

DC-SCM LTPI IP Core provides a solution for minimal wire connection between two FPGAs to provide TDM-based bidirectional communication, aggregating multiple data such as I2C, GPIO and UART to add more flexibility to a customer’s system and board design. This solution is compliant with Datacenter-ready Secure Control Module (DC-SCM) 2.0.

Multiple interfaces tunneling – Supports tunneling of more interfaces such as GPIO, I2C, UART, OEM, and data channel aggregation.

High bandwidth capabilities – Supports up to 800 Mbps LVDS data rate for MachXO3™ family devices.

Features

  • Compliant with OCP DC-SCM 2.0 LTPI 1.0 Specifications
  • Supports Link initialization, discovery, and negotiation
  • Supports Multi-channel Serial Interface and LVDS
  • Supports up to five channels aggregation/disaggregation in total
  • Supports GPIO, I2C, UART, OEM, and Data channel aggregation

Jump to

Block Diagram

Performance and Size

IP Configuration
Target Device LCMXO3L
Configuration Registers Slice LUTs EBRs
LCMXO3L-9400C 6BG484C
IP Mode = SCM
DDR == Enabled
Low Latency I/O == 16
Normal Latency I/O == 16
I2C == 1 (Controller)
UART == 2
OEM == 16
Data Channel == Enabled
2346 1202 2296 6
LCMXO3L-9400C 6BG484C
IP Mode = HPM
DDR == Enabled
Low Latency I/O == 16
Normal Latency I/O == 16
I2C == 1 (Target)
UART == 2
OEM == 32
Data Channel == Enabled
2237 1157 2235 6

Note: Utilization data is generated using a sample IP configuration for LCMXO3L-9400C-6BG484C with Strategy set to default setting.
Number may vary when using a different software version or targeting a different device density, synthesis tool, or speed grade. For Static Timing Analysis, IP is tested in both -5 and -6 speed grade. For better performance in certain cases, user is recommended to run multiple iterations of Place and Route and/or set Optimization Goal to Timing in Strategy Section of SW tool.

Ordering Information

Device Family Part Number
Multi-Site
MachXO3D LTPI-XO3D-UT
MachXO3 LTPI-XO3-UT
Mach-NX LTPI-MNX-UT
MachXO5-NX LTPI-XO5-UT

Evaluate: To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

Purchase: To find out how to purchase the IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
DC-SCM LVDS Tunneling Protocol and Interface IP Core - User Guide
FPGA-IPUG-02200 1.1 9/7/2022 PDF 1.9 MB

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