莱迪思解决方案

Reference Design

GHRD/GSRD参考设计

黄金硬件和软件参考设计（GSRD）包括了使用基于CertusPro-NX Versa开发板开发各种应用所需的组件。

CertusPro-NX, Avant-E 

GHRD, GSRD, RISC-V, AXI4, MPMC, Lattice Automate, Defense 

演示

GHRD/GSRD Demonstration

The Golden Hardware and Software Reference Design comprises of components for developing various kind of applications using CertusPro-NX Versa Board.

CertusPro-NX, Avant-E 

GHRD, GSRD, RISC-V, AXI4, MPMC, Lattice Automate, Defense 

演示

MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

This demo illustrates L-ASC10 integration in a MachXO5-NX design and demonstrates RISC-V SOC interfacing with power sequencing and fault response.

MachXO5-NX 

L-ASC10, RISC-V, Defense, SDR 

演示

莱迪思Sentry MachXO3D可信根演示

完整的位流/固件包可帮助您在采用MachXO3D的莱迪思Sentry演示板上演示和测试符合NIST 800-193规范的PFR解决方案

MachXO3D 

NIST, RISC-V, Lattice Sentry, Security, Defense 

IP Core

RISC-V MC CPU IP核

Propel IP模块：具有可选的定时器和PIC子模块的32位RISC-V处理器核，通过AHB-Lite总线连接到其他Propel各类IP模块。

Certus-N2, MachXO3D, Certus-NX, CrossLink-NX, Avant-E, MachXO5-NX, CertusPro-NX, MachXO3, MachXO2 , Avant-G, Avant-X, MachXO4 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR, Avionics 

IP Core

RISC-V SM CPU IP核

RISC-V SM CPU IP可以在处理数据和指令时处理外部中断。该IP支持RV32I指令集、外部中断和调试，遵循JTAG – IEEE 1149.1标准。

Certus-N2, Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX, MachXO3D, MachXO3, MachXO2 , Avant-G, Avant-X, iCE40 Ultra/UltraLite 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR 

IP Core

RISC-V RX CPU IP核

莱迪思RISC-V RX IP使用32位RISC-V处理器核和多个子模块，在监控外部中断的同时处理数据和指令。

Certus-N2, Avant-E, Avant-G, Avant-X, MachXO5-NX, CrossLink-NX, CertusPro-NX, Certus-NX 

AHB-Lite, Soft Processor, RISC-V, RTOS, Lattice Propel, Defense, Automotive 

IP Core

RISC-V Nano CPU IP Core

The RISC-V Nano CPU IP contains a 32-bit RISC-V processor core that supports the RV32I instruction set and a lightweight interrupt merge controller.

Certus-N2, Avant-E, Avant-G, Avant-X, MachXO5-NX, CrossLink-NX, CertusPro-NX, Certus-NX, MachXO3D, MachXO2 , iCE40 UltraPlus, MachXO4 

Soft Processor, RISC-V, Lattice Propel, Lattice Diamond, Lattice Radiant, Defense, AHB-Lite 

IP Core

RISC-V AXI4 I/O Physical Memory Protection (IOPMP) IP Core

RISC-V I/O Memory Protection IP protects the data in specific memory regions and allows the CPU to control external AXI manager access to AXI subordinates at run-time.

Avant-E, Avant-G, Avant-X, MachXO5-NX, CrossLink-NX, Certus-NX, CertusPro-NX, 莱迪思Propel系统设计环境 

Soft Processor, RISC-V, Lattice Propel, Lattice Diamond, Lattice Radiant, Defense 

Reference Design

Close Loop BLDC Motion Control Reference Design

Implementation of Industrial high-end encoder on real-time position feedback for speed control in the Closed-loop BLDC motor control system

Certus-NX 

BLDC, RISC-V, Avionics 

Reference Design

MPESTI Initiator Reference Design

MPESTI Initiator Reference Design provides the solution template which is compliant with the MPESTI Base Specification.

Avant-E, MachXO5-NX, MachXO3, MachXO3D 

MPESTI, UART, APB, AHB, RISC-V, OCP 

IP Core

FreeRTOS

FreeRTOS software included in Lattice Propel 2022.1 for RISC-V embedded processor available with real-time kernel and set of libraries.

Avant-E, MachXO5-NX, CertusPro-NX, Certus-NX, CrossLink-NX 

Lattice Propel, RTOS, RISC-V 

Reference Design

MachXO5-NX I2C Reference Design

The MachXO5-NX I2C reference design initiates and connects the MachXO5-NX flash programming through the user I2C interface.

MachXO5-NX 

I2C, RISC-V, Soc 

Reference Design

RISC-V RX and LPDDR4 Memory Controller Reference Design

RISC-V RX & LPDDR4 Memory Controller Reference Design shows usage of the RISC-V RX soft IP & LPDDR4 memory controller in Lattice Avant™ & CertusPro™ NX.

Avant-E, CertusPro-NX 

RISC-V, LPDDR4, AXI4, SDRAM, IEEE 1149.1, Lattice Propel 

IP Core

RISC-V AHB-L I/O Physical Memory Protection (IOPMP) IP Core

Lattice Semiconductor’s RISC-V AHB-L IOPMP IP is a standalone memory protection unit that prevents illegal or unexpected access to specific memory regions.

Certus-N2, Avant-E, Avant-G, Avant-X, MachXO5-NX, CertusPro-NX, Certus-NX, CrossLink-NX 

RISC-V, AHB-L, IOPMP, Lattice Propel 

Reference Design

莱迪思Sentry采用MachXO3D的可信根参考设计

该设计采用莱迪思Sentry IP帮助您开发和测试一套完整的符合NIST 800-193规范的PFR解决方案。您还可以对其进行修改满足特定需求。

MachXO3D 

NIST, RISC-V, Lattice Propel, Lattice Sentry, Security, Defense 

Reference Design

莱迪思Mach-NX Sentry可信根参考设计

该设计利用平台固件保护恢复可信根来帮助开发和测试一个完整的符合NIST 800-193标准的安全系统，该系统具有保护、检测和恢复功能。

Mach-NX 

GPIO Control, I2C, RISC-V, SPI, UART, NIST, Lattice Propel, Lattice Sentry, Defense 

IP Core

​​I3C滤波器IP核

莱迪思I3C滤波器IP从总线上的控制器和从设备的角度来看可以起到隐形中继的作用。

MachXO5-NX 

I3C, Bus Controllers, MIPI Bundle, SMBus, RISC-V 

IP Core

RISC-V Single Core Linux (SCL) Processor

RISC-V Single Core Linux processor includes everything required for running Linux on Lattice FPGAs and supports the RV32IMAC and RV32GC architecture.

CertusPro-NX 

RISC-V, Soft Processor, DDR Memories, AHB, AHB-Lite, AMBA, AXI, GPIO Control, UART 

IP Core

SLS I2C Master IP Core

Ease to use I2C Master IP core from SLS. It comes with ready to use HAL driver, reference design and various documents.

CrossLink-NX 

RISC-V, AHB-Lite, I2C