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  • Lattice Sentry Root of Trust Demo for MachXO3D

    Demo

    Lattice Sentry Root of Trust Demo for MachXO3D

    A complete bitstream/firmware package which helps you demonstrate and test a NIST 800-193-compliant PFR solution on the Lattice Sentry Demo Board for MachXO3D
    Lattice Sentry Root of Trust Demo for MachXO3D
  • Lattice Sentry Root of Trust Reference Design for MachXO3D

    Reference Design

    Lattice Sentry Root of Trust Reference Design for MachXO3D

    This design utilizes Lattice Sentry IP to help you develop and test a complete NIST 800-193-compliant PFR solution. You can modify to suit your specific needs.
    Lattice Sentry Root of Trust Reference Design for MachXO3D
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    Propel IP Module: 32-bit RISC-V processor core with optional Timer and PIC sub-modules, connects via AHB-Lite bus to other Propel IP modules and more.
    RISC-V MC CPU IP Core
  • Multi-Channel Motor Control with Predictive Maintenance

    Demo

    Multi-Channel Motor Control with Predictive Maintenance

    This design incorporates a RISC-V CPU and processing subsystem supporting multi-channel Motor Control with Predictive Maintenance.
    Multi-Channel Motor Control with Predictive Maintenance
  • Multi-Channel Motor Control with Predictive Maintenance

    Reference Design

    Multi-Channel Motor Control with Predictive Maintenance

    This design incorporates a RISC-V CPU and processing subsystem supporting multi-channel Motor Control with Predictive Maintenance.
    Multi-Channel Motor Control with Predictive Maintenance
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    The RISC-V SM CPU IP processes data and instructions while considering the external interrupts. The CPU core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • Long Range (LoRa) Wireless

    Reference Design

    Long Range (LoRa) Wireless

    Implement a LoRa compliant device using a tiny iCE40 UltraPlus FPGA, for low-power, low-footprint wireless communication over miles
    Long Range (LoRa) Wireless
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