Lattice Solutions

Reference Design

GHRD/GSRD Reference Design

The Golden Hardware and Software Reference Design comprises of components for developing various kind of applications using CertusPro-NX Versa Board.

CertusPro-NX, Avant-E 

GHRD, GSRD, RISC-V, AXI4, MPMC, Lattice Automate, Defense 

Demo

GHRD/GSRD Demonstration

The Golden Hardware and Software Reference Design comprises of components for developing various kind of applications using CertusPro-NX Versa Board.

CertusPro-NX, Avant-E 

GHRD, GSRD, RISC-V, AXI4, MPMC, Lattice Automate, Defense 

Demo

MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

This demo illustrates L-ASC10 integration in a MachXO5-NX design and demonstrates RISC-V SOC interfacing with power sequencing and fault response.

MachXO5-NX 

L-ASC10, RISC-V, Defense, SDR 

Demo

Lattice Sentry Root of Trust Demo for MachXO3D

A complete bitstream/firmware package which helps you demonstrate and test a NIST 800-193-compliant PFR solution on the Lattice Sentry Demo Board for MachXO3D

MachXO3D 

NIST, RISC-V, Lattice Sentry, Security, Defense 

IP Core

RISC-V MC CPU IP Core

The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).

MachXO3D, Certus-NX, CrossLink-NX, Avant-E, MachXO5-NX, CertusPro-NX, MachXO3, MachXO2, Avant-G, Avant-X 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR 

IP Core

RISC-V SM CPU IP Core

Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.

Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX, MachXO3D, MachXO3, MachXO2, Avant-G, Avant-X 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR 

IP Core

RISC-V RX CPU IP Core

Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.

Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX, Avant-G, Avant-X 

AHB-Lite, Soft Processor, RISC-V, RTOS, Lattice Propel, Defense, Automotive 

IP Core

RISC-V Nano CPU IP Core

The RISC-V Nano CPU IP contains a 32-bit RISC-V processor core that supports the RV32I instruction set and a lightweight interrupt merge controller.

Avant-E, Avant-G, Avant-X, MachXO5-NX, CrossLink-NX, Certus-NX, CertusPro-NX 

Soft Processor, RISC-V, Lattice Propel, Lattice Diamond, Lattice Radiant, Defense, AHB-Lite 

IP Core

RISC-V I/O Physical Memory Protection (IOPMP) IP Core

RISC-V I/O Memory Protection IP protects the data in specific memory regions and allows the CPU to control external AXI manager access to AXI subordinates at run-time.

Avant-E, Avant-G, Avant-X, MachXO5-NX, CrossLink-NX, Certus-NX, CertusPro-NX 

Soft Processor, RISC-V, Lattice Propel, Lattice Diamond, Lattice Radiant, Defense 

Reference Design

Close Loop BLDC Motion Control Reference Design

Implementation of Industrial high-end encoder on real-time position feedback for speed control in the Closed-loop BLDC motor control system

Certus-NX 

BLDC, RISC-V 

IP Core

FreeRTOS

FreeRTOS software included in Lattice Propel 2022.1 for RISC-V embedded processor available with real-time kernel and set of libraries.

Avant-E, MachXO5-NX, CertusPro-NX, Certus-NX, CrossLink-NX 

Lattice Propel, RTOS, RISC-V 

Reference Design

MachXO5-NX I2C Reference Design

The MachXO5-NX I2C reference design initiates and connects the MachXO5-NX flash programming through the user I2C interface.

MachXO5-NX 

I2C, RISC-V, Soc 

Reference Design

RISC-V RX and LPDDR4 Memory Controller Reference Design

RISC-V RX & LPDDR4 Memory Controller Reference Design shows usage of the RISC-V RX soft IP & LPDDR4 memory controller in Lattice Avant™ & CertusPro™ NX.

Avant-E, CertusPro-NX 

RISC-V, LPDDR4, AXI4, SDRAM, IEEE 1149.1, Lattice Propel 

Reference Design

Lattice Sentry Root of Trust Reference Design for MachXO3D

This design utilizes Lattice Sentry IP to help you develop and test a complete NIST 800-193-compliant PFR solution. You can modify to suit your specific needs.

MachXO3D 

NIST, RISC-V, Lattice Propel, Lattice Sentry, Security, Defense 

Reference Design

Lattice Sentry Root of Trust Reference Design for Mach-NX

This design utilizes Platform Firmware Resiliency System Root of Trust to help develop and test a complete NIST 800-193 compliant security system that protects, detects, and recovers.

Mach-NX 

GPIO Control, I2C, RISC-V, SPI, UART, NIST, Lattice Propel, Lattice Sentry, Defense 

IP Core

​​I3C Filter IP Core​

​​The Lattice I3C Filter IP functions as an invisible relay from the point of view of the Controller and Target devices on the bus.​

MachXO5-NX 

I3C, Bus Controllers, MIPI Bundle, SMBus, RISC-V 

IP Core

RISC-V Single Core Linux (SCL) Processor

RISC-V Single Core Linux processor includes everything required for running Linux on Lattice FPGAs and supports the RV32IMAC and RV32GC architecture.

CertusPro-NX 

RISC-V, Soft Processor, DDR Memories, AHB, AHB-Lite, AMBA, AXI, GPIO Control, UART 

IP Core

SLS I2C Master IP Core

Ease to use I2C Master IP core from SLS. It comes with ready to use HAL driver, reference design and various documents.

CrossLink-NX 

RISC-V, AHB-Lite, I2C 

IP Core

USB 2.0 Device Controller IP Core (USB20SF)

USB20SF IP core provides FIFO interface for Data Endpoints while AHB Lite interface for Control Endpoint. This IP core supports High Speed and Full Speed modes

CrossLink-NX 

ARM, RISC-V, Soft Processor, FMC, AHB, AHB-Lite, AXI, Camera, ULPI, USB2 

IP Core

​​USB 3.2 Gen 1 Device Controller IP Core (USB32SF)​

This IP core solution uses the FPGA’s built-in transceiver for USB 3.2 and ULPI PHY for USB 2.0. It supports SuperSpeed, High Speed and Full Speed modes.

CrossLink-NX, CertusPro-NX 

ARM, RISC-V, Soft Processor, FMC, AHB, AHB-Lite, AXI, USB Type-C, USB3, Camera, Image Processing, MIPI