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  • Lattice Sentry Root of Trust Demo for MachXO3D

    Demo

    Lattice Sentry Root of Trust Demo for MachXO3D

    A complete bitstream/firmware package which helps you demonstrate and test a NIST 800-193-compliant PFR solution on the Lattice Sentry Demo Board for MachXO3D
    Lattice Sentry Root of Trust Demo for MachXO3D
  • Lattice Sentry Root of Trust Reference Design for MachXO3D

    Reference Design

    Lattice Sentry Root of Trust Reference Design for MachXO3D

    This design utilizes Lattice Sentry IP to help you develop and test a complete NIST 800-193-compliant PFR solution. You can modify to suit your specific needs.
    Lattice Sentry Root of Trust Reference Design for MachXO3D
  • Lattice Sentry Root of Trust Reference Design for Mach-NX

    Reference Design

    Lattice Sentry Root of Trust Reference Design for Mach-NX

    This design utilizes Platform Firmware Resiliency System Root of Trust to help develop and test a complete NIST 800-193 compliant security system that protects, detects, and recovers.
    Lattice Sentry Root of Trust Reference Design for Mach-NX
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    Propel IP Module: 32-bit RISC-V processor core with optional Timer and PIC sub-modules, connects via AHB-Lite bus to other Propel IP modules and more.
    RISC-V MC CPU IP Core
  • eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)

    IP Core

    eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)

    This IP core solution uses the CL-NX FPGA’s built-in transceiver for USB 3.1 and ULPI PHY for USB 2.0. It supports SuperSpeed, High Speed and Full Speed modes.
    eUSB 3.1 Gen 1 Device Controller IP Core (eUSB31SF)
  • USB 2.0 Device Controller IP Core (USB20SF)

    IP Core

    USB 2.0 Device Controller IP Core (USB20SF)

    USB20SF IP core provides FIFO interface for Data Endpoints while AHB Lite interface for Control Endpoint. This IP core supports High Speed and Full Speed modes
    USB 2.0 Device Controller IP Core (USB20SF)
  • Multi-Channel Motor Control with Predictive Maintenance

    Reference Design

    Multi-Channel Motor Control with Predictive Maintenance

    This design incorporates a RISC-V CPU and processing subsystem supporting multi-channel Motor Control with Predictive Maintenance.
    Multi-Channel Motor Control with Predictive Maintenance
  • Multi-Channel Motor Control with Predictive Maintenance

    Demo

    Multi-Channel Motor Control with Predictive Maintenance

    This design incorporates a RISC-V CPU and processing subsystem supporting multi-channel Motor Control with Predictive Maintenance.
    Multi-Channel Motor Control with Predictive Maintenance
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    The RISC-V SM CPU IP processes data and instructions while considering the external interrupts. The CPU core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • Ikva ML Accelerator IP Core

    IP Core

    Ikva ML Accelerator IP Core

    Powerful, scalable ML accelerator supporting 8-bit CNNs and 1-bit Binarized Neural Networks (BNNs), a rich software stack and computer vision models.
    Ikva ML Accelerator IP Core
  • DPC CCM – Color correction

    IP Core

    DPC CCM – Color correction

    DPC CCM is designed to reduce the difference between the spectral characteristics of an image sensor and the spectral response of the human eye.
    DPC CCM – Color correction
  • DPC Color Conversion

    IP Core

    DPC Color Conversion

    DPC Color Conversion allows real-time conversion of the RGB colour space into the YCbCr colour space.
    DPC Color Conversion
  • DPC Convolution 3x3

    IP Core

    DPC Convolution 3x3

    DPC Conv3x3 applies a kernel to a video stream, in real time, in order to obtain spatial filtering such as Sobel, Gaussian, Laplacian and more.
    DPC Convolution 3x3
  • DPC Debayer

    IP Core

    DPC Debayer

    DPC Debayer reconstructs RGB images, in real time, from RAW data captured by an image sensor.
    DPC Debayer
  • DPC Defective Pixel Correction

    IP Core

    DPC Defective Pixel Correction

    DPC Defective detects and corrects defective pixels in applications with a Bayer pattern image sensor.
    DPC Defective Pixel Correction
  • DPC Gamma RGB

    IP Core

    DPC Gamma RGB

    DPC Gamma RGB is the IP dedicated to correcting, in real time, the gamma transformation curve of an incoming video stream.
    DPC Gamma RGB
  • DPC HDR

    IP Core

    DPC HDR

    DPC HDR obtains an HDR (High Dynamic Range) output stream from two separate input streams (high exposure and low exposure).
    DPC HDR
  • DPC Statistics RGB

    IP Core

    DPC Statistics RGB

    DPC Statistics RGB provides, for each frame, the histograms of the R, G and B channels.
    DPC Statistics RGB
  • DPC Statistics YCbCr

    IP Core

    DPC Statistics YCbCr

    DPC Statistics YCbCr provides, for each frame, the histograms of the Y, Cb and Cr channels.
    DPC Statistics YCbCr
  • DPC Subsampler 4:2:2

    IP Core

    DPC Subsampler 4:2:2

    DPC Subsampler422 is a simple IP block for real-time conversion of a YCbCr 4:4:4 video stream to a YCbCr 4:2:2 stream.
    DPC Subsampler 4:2:2
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