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  • RISC-V RX and LPDDR4 Memory Controller Reference Design

    Reference Design

    RISC-V RX and LPDDR4 Memory Controller Reference Design

    RISC-V RX & LPDDR4 Memory Controller Reference Design shows usage of the RISC-V RX soft IP & LPDDR4 memory controller in Lattice Avant™ & CertusPro™ NX.
    Avant-E, CertusPro-NX 
    RISC-V, LPDDR4, AXI4, SDRAM, IEEE 1149.1, Lattice Propel 
    RISC-V RX and LPDDR4 Memory Controller Reference Design
  • BSCAN - Multiple Port Linker (BSCAN2)

    Reference Design

    BSCAN - Multiple Port Linker (BSCAN2)

    Implements an IEEE 1149.1 compliant Boundary Scan port on an FPGA. Multiple scan ports are linked together feeing into the IEEE 1149.1 port.
    MachXO, MachXO2, ispMACH 4000ZE, ispMACH 4000V/B/C/Z, LatticeXP2, ECP5 / ECP5-5G 
    IEEE 1149.1, Boundary Scan 
    BSCAN - Multiple Port Linker (BSCAN2)
  • BSCAN - Multiple Port Addressable Buffer (BSCAN-1)

    Reference Design

    BSCAN - Multiple Port Addressable Buffer (BSCAN-1)

    A multiple boundary scan test access port (TAP) addressable buffer function that can be accessed through a standard IEEE 1149.1 interface
    LatticeXP2, ispMACH 4000ZE, MachXO, ispMACH 4000V/B/C/Z, Platform Manager 
    Boundary Scan, IEEE 1149.1, TOR Switch 
    BSCAN - Multiple Port Addressable Buffer (BSCAN-1)
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