莱迪思解决方案

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  • RISC-V MC CPU IP核

    IP Core

    RISC-V MC CPU IP核

    Propel IP模块:具有可选的定时器和PIC子模块的32位RISC-V处理器核,通过AHB-Lite总线连接到其他Propel各类IP模块。
    RISC-V MC CPU IP核
  • RISC-V SM CPU IP核

    IP Core

    RISC-V SM CPU IP核

    RISC-V SM CPU IP可以在处理数据和指令时处理外部中断。该IP支持RV32I指令集、外部中断和调试,遵循JTAG – IEEE 1149.1标准。
    RISC-V SM CPU IP核
  • RISC-V RX CPU IP核

    IP Core

    RISC-V RX CPU IP核

    莱迪思RISC-V RX IP使用32位RISC-V处理器核和多个子模块,在监控外部中断的同时处理数据和指令。
    RISC-V RX CPU IP核
  • RISC-V Nano CPU IP Core

    IP Core

    RISC-V Nano CPU IP Core

    The RISC-V Nano CPU IP contains a 32-bit RISC-V processor core that supports the RV32I instruction set and a lightweight interrupt merge controller.
    RISC-V Nano CPU IP Core
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory (TCM) IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Tightly-Coupled Memory (TCM) IP Core
  • RISC-V AXI4 I/O Physical Memory Protection (IOPMP) IP Core

    IP Core

    RISC-V AXI4 I/O Physical Memory Protection (IOPMP) IP Core

    RISC-V I/O Memory Protection IP protects the data in specific memory regions and allows the CPU to control external AXI manager access to AXI subordinates at run-time.
    RISC-V AXI4 I/O Physical Memory Protection (IOPMP) IP Core
  • Lattice Sentry SMBus Mailbox IP Core

    IP Core

    Lattice Sentry SMBus Mailbox IP Core

    SMBus, a two-wire interface that support fairness arbitration and compatible with AHB-Lite specification. Target devices are Mach-NX and MachXO3D.
    Lattice Sentry SMBus Mailbox IP Core
  • PIC IP Core

    IP Core

    PIC IP Core

    Lattice Semiconductor PIC soft IP with configurable 1~8 interrupt inputs and 32-bit AHB-L interface for Mach-NX FPGA
    PIC IP Core
  • SFB Interface IP Core

    IP Core

    SFB Interface IP Core

    SFB allow access to AHB-L CPLD block , management CPU recovery circuit and Flash sector for read/write.
    SFB Interface IP Core
  • 莱迪思Sentry PLD接口IP核

    IP Core

    莱迪思Sentry PLD接口IP核

    莱迪思半导体客户可编程逻辑器件(PLD)实现了发送和接收消息的双向邮箱功能。
    莱迪思Sentry PLD接口IP核
  • Lattice Sentry I2C Filter IP Core

    IP Core

    Lattice Sentry I2C Filter IP Core

    Sentry I2C Filter IP Core provides an interface between I2C bus devices and a host processor while protecting against common I2C bus vulnerabilities.
    Lattice Sentry I2C Filter IP Core
  • 莱迪思Sentry ESB Mux IP核用于MachXO3D

    IP Core

    莱迪思Sentry ESB Mux IP核用于MachXO3D

    用于莱迪思Sentry的Propel IP模块:访问MachXO3D的嵌入式安全模块(ESB)的同时进行内部加密操作
    莱迪思Sentry ESB Mux IP核用于MachXO3D
  • 莱迪思Sentry I2C监视器IP核用于MachXO3D

    IP Core

    莱迪思Sentry I2C监视器IP核用于MachXO3D

    用于莱迪思Sentry的Propel IP模块:监视I2C总线上的通信,识别和阻止潜在的非法通信。
    莱迪思Sentry I2C监视器IP核用于MachXO3D
  • 莱迪思Sentry QSPI Streamer IP核用于MachXO3D

    IP Core

    莱迪思Sentry QSPI Streamer IP核用于MachXO3D

    用于莱迪思Sentry的Propel IP模块:提供高速SPI存储器访问便于可信根平台操作中的固件身份验证
    莱迪思Sentry QSPI Streamer IP核用于MachXO3D
  • 莱迪思Sentry QSPI监视器IP核用于MachXO3D

    IP Core

    莱迪思Sentry QSPI监视器IP核用于MachXO3D

    用于莱迪思Sentry的Propel IP模块:监视SPI/QSPI总线上的通信,可识别和阻止潜在的非法通信。
    莱迪思Sentry QSPI监视器IP核用于MachXO3D
  • AXI4 to APB Bridge Module

    IP Core

    AXI4 to APB Bridge Module

    The Lattice Semiconductor AXI4 to APB Bridge Module provides an interface between the high-speed AXI4 and APB.
    AXI4 to APB Bridge Module
  • AXI4 to AHB-Lite Bridge Module IP Core

    IP Core

    AXI4 to AHB-Lite Bridge Module IP Core

    Lattice Semiconductor AXI4 to AHB-Lite Bridge Module provides an interface between the high-speed AXI4 and AHB-Lite.
    AXI4 to AHB-Lite Bridge Module IP Core
  • FreeRTOS

    IP Core

    FreeRTOS

    FreeRTOS software included in Lattice Propel 2022.1 for RISC-V embedded processor available with real-time kernel and set of libraries.
  • LVDS Tunneling Protocol and Interface Reference Design

    Reference Design

    LVDS Tunneling Protocol and Interface Reference Design

    The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.
    LVDS Tunneling Protocol and Interface Reference Design
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