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  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
    RISC-V MC CPU IP Core
  • RISC-V RX CPU IP Core

    IP Core

    RISC-V RX CPU IP Core

    Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
    RISC-V RX CPU IP Core
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Tightly-Coupled Memory (TCM) IP Core
  • Lattice Sentry I2C Filter IP Core

    IP Core

    Lattice Sentry I2C Filter IP Core

    Sentry I2C Filter IP Core provides an interface between I2C bus devices and a host processor while protecting against common I2C bus vulnerabilities.
    Lattice Sentry I2C Filter IP Core
  • Lattice Sentry PLD Interface IP Core

    IP Core

    Lattice Sentry PLD Interface IP Core

    Lattice Semiconductor Customer Programmable Logic Devices (PLD)implements a bidirectional mailbox for sending and receiving messages.
    Lattice Sentry PLD Interface IP Core
  • Lattice Sentry SMBus Mailbox IP Core

    IP Core

    Lattice Sentry SMBus Mailbox IP Core

    SMBus, a two-wire interface that support fairness arbitration and compatible with AHB-Lite specification. Target devices are Mach-NX and MachXO3D.
    Lattice Sentry SMBus Mailbox IP Core
  • PIC IP Core

    IP Core

    PIC IP Core

    Lattice Semiconductor PIC soft IP with configurable 1~8 interrupt inputs and 32-bit AHB-L interface for Mach-NX FPGA
    PIC IP Core
  • SFB Interface IP Core

    IP Core

    SFB Interface IP Core

    SFB allow access to AHB-L CPLD block , management CPU recovery circuit and Flash sector for read/write.
    SFB Interface IP Core
  • Lattice Sentry Root of Trust Reference Design for MachXO3D

    Reference Design

    Lattice Sentry Root of Trust Reference Design for MachXO3D

    This design utilizes Lattice Sentry IP to help you develop and test a complete NIST 800-193-compliant PFR solution. You can modify to suit your specific needs.
    Lattice Sentry Root of Trust Reference Design for MachXO3D
  • Lattice Sentry ESB Mux IP Core for MachXO3D

    IP Core

    Lattice Sentry ESB Mux IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Enables access the MachXO3D embedded security block (ESB) simultaneously with internal crytographic operations
    Lattice Sentry ESB Mux IP Core for MachXO3D
  • Lattice Sentry I2C Monitor IP Core for MachXO3D

    IP Core

    Lattice Sentry I2C Monitor IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Monitors traffic on I2C bus to identify and block potentially illegal traffic.
    Lattice Sentry I2C Monitor IP Core for MachXO3D
  • Lattice Sentry QSPI Monitor IP Core for MachXO3D

    IP Core

    Lattice Sentry QSPI Monitor IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Monitors traffic on SPI/QSPI bus to identify and block potentially illegal traffic.
    Lattice Sentry QSPI Monitor IP Core for MachXO3D
  • Lattice Sentry QSPI Streamer IP Core for MachXO3D

    IP Core

    Lattice Sentry QSPI Streamer IP Core for MachXO3D

    Propel IP Module for Lattice Sentry: Provides fast SPI memory access for firmware authentication as part fo Platform Root of Trust operation
    Lattice Sentry QSPI Streamer IP Core for MachXO3D
  • Lattice Sentry Root of Trust Reference Design for Mach-NX

    Reference Design

    Lattice Sentry Root of Trust Reference Design for Mach-NX

    This design utilizes Platform Firmware Resiliency System Root of Trust to help develop and test a complete NIST 800-193 compliant security system that protects, detects, and recovers.
    Lattice Sentry Root of Trust Reference Design for Mach-NX
  • ​​Lattice Sentry PFR Platform Root of Trust (PRoT) Reference Design​

    Reference Design

    ​​Lattice Sentry PFR Platform Root of Trust (PRoT) Reference Design​

    ​​Lattice Sentry PFR Platform Root of Trust design support Mach-NX and MachXO5-NX devices with low-density FPGA and enhanced user-mode security functions.​
    ​​Lattice Sentry PFR Platform Root of Trust (PRoT) Reference Design​
  • Lattice Sentry 2.2 BKC Reference Design

    Reference Design

    Lattice Sentry 2.2 BKC Reference Design

    The Lattice Sentry Best-Known Configuration (BKC) Reference Design provides a basic framework to implement a PFR design.
    Lattice Sentry 2.2 BKC Reference Design
  • FreeRTOS

    IP Core

    FreeRTOS

    FreeRTOS software included in Lattice Propel 2022.1 for RISC-V embedded processor available with real-time kernel and set of libraries.
  • LVDS Tunneling Protocol and Interface Reference Design

    Reference Design

    LVDS Tunneling Protocol and Interface Reference Design

    The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.
    LVDS Tunneling Protocol and Interface Reference Design
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