RISC-V for RTOS Applications

The Lattice Semiconductor RISC-V RX soft IP contains a 32-bit RISC-V processor core and several submodules – Platform Level Interrupt Controller (PLIC), Core Local Interrupter (CLINT), and Watchdog. The CPU core supports the RV32IMC instruction set and debug feature which is JTAG – IEEE 1149.1 compliant. The modules outside are accessed by the processor core using AXI or Local Bus Interface.

The design is implemented in Verilog HDL. It can be configured and generated using the Lattice Propel™ Builder software. It supports Lattice Avant™, MachXO5™-NX, Certus™-NX, CertusPro™-NX, and CrossLink™-NX FPGA devices.

Supports the IEEE-1149.1 JTAG Debug Logic - The processor core supports the IEEE-1149.1 JTAG debug logic with two hardware breakpoints. In the revised RX core, for Lattice Avant family devices, the debug feature only supports the soft JTAG mode. For other family devices, the debug feature only supports the hard JTAG mode.

Physical Memory Protection (PMP) Unit - The Physical Memory Protection (PMP) unit provides machine mode control registers to limit the access of different regions of physical memory with different privileges (read, write, execute) for RV32 systems.

Custom Function Unit – Custom Function Unit (CFU) is a kind of light-weight and customized arithmetic accelerator. With the support of CFU Logic Interface (CFU-LI), customers can integrate CFUs into their SoC and insert Custom Functions (CF) to deploy CFU hardware, according to actual solution demand.


  • RV32IMC instruction set
  • Five stage pipeline
  • All three privilege modes supported: Machine mode, Supervisor mode, and User mode
  • Instruction Cache and Data Cache
  • Support for the AXI4 bus standard for data port

Block Diagram

Resource Utilization

Device Configuration LUTs Registers sysMEM EBRs
Avant Processor core 5013 2481 17
Processor core + PLIC + CLINT + UART + CFU-LI + Debug 6181 3447 17
CertusPro-NX Processor core 5150 2549 18
Processor core + PLIC + CLINT + UART + CFU-LI + Debug 6577 3762 18

Note: Resource utilization characteristics are generated using Lattice Radiant 2022.1 software.


Quick Reference
Select All
RISC-V RX CPU IP - Lattice Propel Builder 2023.1
FPGA-IPUG-02230 1.0 6/29/2023 PDF 656.1 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.