RISC-V RX CPU IP Core

RISC-V for RTOS Applications

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The Lattice Semiconductor RISC-V RX soft IP contains a 32-bit RISC-V processor core and several submodules – Platform Level Interrupt Controller (PLIC), Core Local Interrupter (CLINT), and Watchdog. The CPU core supports the RV32IMC instruction set and debug feature which is JTAG – IEEE 1149.1 compliant. The modules outside are accessed by the processor core using AXI or Local Bus Interface.

The design is implemented in Verilog HDL. It can be configured and generated using the Lattice Propel™ Builder software. It supports Lattice Avant™, MachXO5™-NX, Certus™-NX, CertusPro™-NX, and CrossLink™-NX FPGA devices.

Supports the IEEE-1149.1 JTAG Debug Logic - The processor core supports the IEEE-1149.1 JTAG debug logic with two hardware breakpoints. In the revised RX core, for Lattice Avant family devices, the debug feature only supports the soft JTAG mode. For other family devices, the debug feature only supports the hard JTAG mode.

Physical Memory Protection (PMP) Unit - The Physical Memory Protection (PMP) unit provides machine mode control registers to limit the access of different regions of physical memory with different privileges (read, write, execute) for RV32 systems.

Custom Function Unit – Custom Function Unit (CFU) is a kind of light-weight and customized arithmetic accelerator. With the support of CFU Logic Interface (CFU-LI), customers can integrate CFUs into their SoC and insert Custom Functions (CF) to deploy CFU hardware, according to actual solution demand.

Features

  • RV32IMC instruction set
  • Five stage pipeline
  • All three privilege modes supported: Machine mode, Supervisor mode, and User mode
  • Instruction Cache and Data Cache
  • Support for the AXI4 bus standard for data port

Block Diagram

Resource Utilization

Device Configuration LUTs Registers sysMEM EBRs
Avant Processor core 8673 4537 20
Processor core + PLIC + CLINT + UART + CFU-LI + Debug 9570 5441 20
CertusPro-NX Processor core 8846 4813 21
Processor core + PLIC + CLINT + UART + CFU-LI + Debug 9827 5718 21

Note: Resource utilization characteristics are generated using Lattice Radiant 2022.1 software.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
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RISC-V RX CPU IP Core - User Guide
FPGA-IPUG-02241 1.0 12/5/2023 PDF 908.6 KB

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