RISC-V RX CPU IP Core

RISC-V for RTOS Applications

The Lattice Semiconductor RISC-V RX soft IP contains a 32-bit RISC-V processor core and several submodules – Platform Level Interrupt Controller (PLIC), Core Local Interrupter (CLINT), and Watchdog. The CPU core supports the RV32IMACF instruction set and the debug feature which is JTAG – IEEE 1149.1 compliant.

Resource Utilization details are available in the IP Core User Guide.

Features

  • RV32IMACF instruction set
  • Five-stage pipeline
  • Three privilege modes supported: Machine mode, Supervisor mode, and User mode
  • Three processor modes supported: Advanced mode, Balanced mode and Lite mode
  • Instruction Cache and Data Cache

Block Diagram

Ordering Information

The RISC-V RX CPU IP Core is provided at no additional cost with Lattice Propel Builder.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
RISC-V RX CPU IP - Lattice Propel Builder 2025.2 User Guide
FPGA-IPUG-02302 1.0 12/11/2025 PDF 1.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
RISC-V RX CPU IP - Lattice Propel Builder 2025.2 User Guide
FPGA-IPUG-02302 1.0 12/11/2025 PDF 1.4 MB

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