The Lattice Semiconductor RISC-V I/O Physical Memory Protection (IOPMP) IP is a separate physical memory protection unit that prevents illegal or unexpected access to some specific regions. These regions can be accessed by the RISC-V CPU but should not be accessed by some controllers, such as DMA or Ethernet.
The design is implemented using Verilog HDL, and it can be configured and generated using the Lattice Propel™ Builder software. It supports iCE40 UltraPlus™, Lattice Avant™, MachXO5™-NX, CrossLink™-NX, Certus™-NX, CertusPro™-NX, MachXO3D™, MachXO3™, and MachXO2™ FPGA devices.
Resource Utilization details are available in the RISC-V I/O Physical Memory Protection User Guide.