RISC-V I/O Physical Memory Protection (IOPMP) IP Core

Dedicated Memory Protection Unit to Prevent Illegal Access to Regions

The Lattice Semiconductor RISC-V I/O Physical Memory Protection (IOPMP) IP is a separate physical memory protection unit that prevents illegal or unexpected access to some specific regions. These regions can be accessed by the RISC-V CPU but should not be accessed by some controllers, such as DMA or Ethernet.

The design is implemented using Verilog HDL, and it can be configured and generated using the Lattice Propel™ Builder software. It supports iCE40 UltraPlus™, Lattice Avant™, MachXO5™-NX, CrossLink™-NX, Certus™-NX, CertusPro™-NX, MachXO3D™, MachXO3™, and MachXO2™ FPGA devices.

Resource Utilization details are available in the RISC-V I/O Physical Memory Protection User Guide.

Features

  • AXI4 interface bridge
  • AXI-Lite interface memory-mapped registers
  • Compact-K model-based controller
  • Lightweight interrupt merge controller module
  • Up to four IOPMP entries with TOR support

Jump to

Block Diagram

Ordering Information

The RISC-V I/O Physical Memory Protection IP Core is provided at no additional cost with Lattice Propel Builder.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
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RISC-V I/O Physical Memory Protection IP - Lattice Propel Builder 2024.2 User Guide
FPGA-IPUG-02272 1.0 12/20/2024 PDF 392.3 KB

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