Lattice Solutions

Everything you need to quickly and easily complete your design

Our system is going under maintenance starting February 14, 2025 at 6:00 PM Pacific and ending February 15, 2025 at 12:00 AM Pacific. During this window, the website may not be reachable. For immediate assistance, please contact techsupport@latticesemi.com.
Share This Result >

Narrow Your Results



Solution Type



Device Support






















Tags



























Providers
Clear All
  • RISC-V Nano CPU IP Core

    IP Core

    RISC-V Nano CPU IP Core

    The RISC-V Nano CPU IP contains a 32-bit RISC-V processor core that supports the RV32I instruction set and a lightweight interrupt merge controller.
    RISC-V Nano CPU IP Core
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory (TCM) IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Tightly-Coupled Memory (TCM) IP Core
  • RISC-V I/O Physical Memory Protection (IOPMP) IP Core

    IP Core

    RISC-V I/O Physical Memory Protection (IOPMP) IP Core

    RISC-V I/O Memory Protection IP protects the data in specific memory regions and allows the CPU to control external AXI manager access to AXI subordinates at run-time.
    RISC-V I/O Physical Memory Protection (IOPMP) IP Core
  • DC-SCM LVDS Tunneling Protocol and Interface IP Core

    IP Core

    DC-SCM LVDS Tunneling Protocol and Interface IP Core

    LTPI IP Core is an Open Computer Project Data Center – Secure Control Module Standards compatible solution which is introduced in the DC-SCM 2.0 Specification.
    DC-SCM LVDS Tunneling Protocol and Interface IP Core
  • AXI Register Slice IP Core

    IP Core

    AXI Register Slice IP Core

    The AXI Register Slice connects the AXI subordinate to the AXI manager by introducing pipeline stages in between to close the timing in critical paths.
    AXI Register Slice IP Core
  • Flash Access IP Core

    IP Core

    Flash Access IP Core

    The Flash Access for MachXO5-NX IP Core enables you to perform write and read access to the internal flash memory of LFMXO5-25 device.
    Flash Access IP Core
  • Avant MPPHY Module

    IP Core

    Avant MPPHY Module

    The MPPHY Module supports the most common high-speed SERDES protocols used for inter-chip connectivity.
    Avant MPPHY Module
  • Page 1 of 1
    First Previous
    1
    Next Last