Flash Access IP Core

Enables Write and Read Access to the Internal Flash Memory

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The Flash Access for MachXO5-NX IP Core enables you to perform write and read access to the internal flash memory of LFMXO5-25 device. The write and read access is performed through the LMMI interface. It consists of two sub-blocks Flash Access Core and OSCILLATOR. Flash Access Core receives the LMMI slave interface access and performs the access to the internal flash memory.

Block Partitioning - Users can modify the partition sizes by changing the attributes prior to IP generation, and they have five options for configuring each of the three CFGx/UFMx partition sizes.

Check Status Sequence - This function is used to check if Flash access IP is busy or not. Users should use this function to ensure that the flash access IP is not busy before performing other functions.

Erase Sequence - This function is used to set all the memory within the specified sector/block to erased state. User should use this function to ensure that the memory location is in erased state prior to performing write access.

On-chip Flash Erase Sequence - This function is used to set the whole on-chip flash to erased state.

Features

  • Supports LMMI interface
  • Supports initial user data to be programmed into the flash memory
  • Supports up to 50 MHz input clock frequency
  • Supports Write Access Sequences
  • This is only supported in MachXO5-NX device

Block Diagram

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
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Flash Access IP Core - User Guide
FPGA-IPUG-02171 1.5 4/7/2024 PDF 1.9 MB

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