Flash Access IP Core

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The Flash Access soft IP enables you to perform write and read access to the internal flash memory of LFMXO5 device. The write and read access is performed through the LMMI interface.

Block Partitioning - Flash memory of LFMXO5 can modify the partition sizes by changing the attributes prior to IP generation.

Check status sequence - Allows to check if the Flash access is busy or not before performing other functions.


  • Supports LMMI interface
  • Supports initial user data to be programmed into the flash memory
  • Supports up to 133 MHz input clock frequency
  • Only supported in LFMXO5 devices

Block Diagram


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Flash Access IP Core - Lattice Radiant Software
FPGA-IPUG-02171 1.0 6/1/2022 PDF 978.8 KB

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