Flash Access IP Core

Enables Write and Read Access to the Internal Flash Memory

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The Flash Access IP core for MachXO5™-NX devices enables you to perform write and read access to the internal flash memory of LFMXO5-25, LFMXO5-55T, and LFMXO5-100T devices. The write and read access are performed through the LMMI interface.

Resource Utilization details are available in the IP Core User Guide.

Features

  • Supports LMMI interface.
  • Supports initial user data to be programmed into the flash memory.
  • Supports up to 50 MHz input clock frequency.
  • Optional LMMI interface for configuration access.
  • This is only supported in LFMXO5-25, LFMXO5-55T, and LFMXO5-100T devices.

Block Diagram

Flash Access IP Core Block DiagramExpand Image

Ordering Information

The Flash Access IP is provided at no additional cost with the Lattice Radiant software.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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Flash Access IP Core - User Guide
FPGA-IPUG-02171 1.8 1/27/2025 PDF 2.1 MB
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Flash Access IP Release Notes
FPGA-RN-02064 1.0 12/20/2024 PDF 220.2 KB

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