Data Center Switches

NIST compliant, Secure, Scalable - Control, Power and Thermal management PLD

Modern-day switches are required to implement security in hardware to ensure end-to-end security to combat the presence of malicious actors in the supply chain. To meet the ever increasing demand on data throughput, the main switch and control processor are becoming more complex and with increased TDP. This makes the power management and thermal management a lot more complex. With the increased number of communication ports, the control PLD is expected to control many I2C channels, LEDs and sense more signals.

  • Standardized, scalable control PLD family with wide range of density and I/O options
  • Lattice’s PFR Stack enables integration of Platform Firmware Resilience (PFR) function to the Control PLD
  • Integrates power and thermal management functions

Jump to

Block Diagram

Switches

Example Use Cases

Control PLD in the CPU

  • Control PLD for sequencing and side-channel logic, SGPIO
  • Secure Platform RoT for Platform Firmware Resilience (CPU)
    • Supply Chain Protection
    • RTS- Encryption Key Storage, data sealing (network usage logs)

Control PLD in Switch Fabric

  • Control PLD + PM for sequencing, glue logic
  • Control interface for multi-port card
  • Secure Platform RoT
    • PFR - Switch SoC, BMC and CPU Firmware(ComExp)
    • Onboarding of multi-port card

CPLD in Multi-port

  • Control PLD + PM for sequencing, glue logic
  • Control Interface for multi-port card
  • Secure Platform RoT
    • PFR - Switch SoC, BMC and CPU Firmware(ComExp)
    • Onboarding of multi-port card

Overall Power & Thermal Management

  • Precision power monitoring with telemetry support
  • Accurate temperature monitoring
  • Fan control
  • Power supply trimming and margining
  • Fault log with time stamp

Reference Designs

8N1 UART Transceiver Reference Design

Reference Design

8N1 UART Transceiver Reference Design

8-bit data, no parity, and 1 stop bit Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel and parallel to serial conversions on data characters received from a peripheral device or CPU
8N1 UART Transceiver Reference Design
Soft I2C Bus Master

Reference Design

Soft I2C Slave Peripheral

Reference Design

Demo

Power Sequencing with Fault Logging Demo

Demo

Power Sequencing with Fault Logging Demo

Uses L-ASC10 to monitor, sequence four separate Power Planes from a central control point. Logs faults with timestamps. Expandable.
Power Sequencing with Fault Logging Demo
Soft I2C Master and Slave – Simple Write and Read

Demo

Soft I2C Master and Slave – Simple Write and Read

Demonstrates the operation of an I2C Master and Slave doing simple write and read of data.
Soft I2C Master and Slave – Simple Write and Read
Generic Soft SPI Master Controller Demonstration

Demo

Generic Soft SPI Master Controller Demonstration

This demo implements the Generic Soft SPI Master Controller Reference Design by performing simple transactions to the external SPI Flash device found in the MachXO3-9400 Development Board
Generic Soft SPI Master Controller Demonstration

IP Cores

RISC-V MC CPU IP Core

IP Core

RISC-V MC CPU IP Core

The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
RISC-V MC CPU IP Core
RISC-V SM CPU IP Core

IP Core

RISC-V SM CPU IP Core

Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
RISC-V SM CPU IP Core
I3C スレーブ IP コア

IP Core

I3C スレーブ IP コア

CrossLink-NX 用ラティス I3C インタフェースは、バスが使用する電力を大幅に効率化しながら、I2C よりも 10 倍以上の速度向上を実現します。
I3C スレーブ IP コア
I3C マスタ IP コア

IP Core

I3C マスタ IP コア

CrossLink-NX 用 I3C インタフェースは、バスが使用する電力を大幅に効率化しながら、I2C よりも 10 倍以上の速度向上を実現します。
I3C マスタ IP コア
AHB-Lite Interconnect Module

IP Core

AHB-Lite Interconnect Module

A fully parameterized soft IP, high performance, low latency interconnect fabric for AMBA 3 AHB-Lite based systems, enabling one or more managers to be connected to one or more subordinates.
AHB-Lite Interconnect Module

Development Kits & Boards

Board

ECP5評価ボード

99米ドルで発売中のECP5評価ボードは85K LUTを備えたECP5-5G FPGAを搭載し、FPGA上のほとんどのI/OとSERDESに容易にアクセスでき、ユーザビリティを拡大するためArduino、Raspberry Piと汎用ヘッダーを内臓しています。
 
MachXO3D Breakout Board

Board

MachXO3D Breakout Board

Small low-cost board with generous access to MachXO3D FPGA IO for general purpose evaluation and development
MachXO3D Breakout Board
MachXO3D Development Board

Board

MachXO3D Development Board

General purpose evaluation and development for MachXO3D with generous IO access and multiple expansion connectors RaspberryPi, Arduino, Lattice Versa, and more.
MachXO3D Development Board
ECP5 Versa 開発キット

Board

ECP5 Versa 開発キット

ECP5 Versa開発キットでPCI Express,、Gigabit Ethernet、DDR3、汎用Serdesパフォーマンスを含むECP5の主要機能の迅速な評価が可能
ECP5 Versa 開発キット
LPTM21L Evaluation Board

Board

Support

技術サポート

技術サポートが必要な方はこちら

品質と信頼性

品質と信頼性に関する資料はこちら